Datasheet

26
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
7.1.4 ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O
clocks in order to reduce noise generated by their digital circuitry. This gives more accurate
ADC conversion results.
7.2 Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the Atmel
®
AVR
®
clock generator, and
routed to the appropriate modules.
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from power-down or power-save, the selected clock source is used to time the
start-up, ensuring stable oscillator operation before instruction execution starts. When the
CPU starts from reset, there is an additional delay allowing the power to reach a stable level
before commencing normal operation. The watchdog oscillator is used for timing this real-time
part of the start-up time. The number of WDT oscillator cycles used for each time-out is shown
in Table 7-2 on page 26.
7.3 Default Clock Source
The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The
default clock source setting is therefore the Internal RC Oscillator running at 8.0MHz with lon-
gest start-up time and an initial system clock prescaling of 8, resulting in 1.0MHz system clock.
This default setting ensures that all users can make their desired clock source setting using an
In-System or High-voltage Programmer.
Table 7-1. Device Clocking Options Select
(1)
Device Clocking Option CKSEL3..0
External Clock 0000
Calibrated Internal RC Oscillator 8.0MHz 0010
Watchdog Oscillator 128kHz 0100
External Low-frequency Oscillator 0110
External Crystal/Ceramic Resonator 1000-1111
Reserved 0101, 0111, 0011,0001
Table 7-2. Number of Watchdog Oscillator Cycles
Typ Time-out Number of Cycles
4ms 512
64ms 8K (8,192)