Datasheet

24
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM read enable signal, EERE, is the read strobe for the EEPROM. When the cor-
rect address is set up in the EEAR register, the EERE bit must be written to logical one to
trigger the EEPROM read. The EEPROM read access takes one instruction, and the
requested data are available immediately. When the EEPROM is read, the CPU is halted for
four cycles before the next instruction is executed. The user should poll the EEPE bit before
starting the read operation. If a write operation is in progress, it is not possible to read the
EEPROM or change the EEAR register.
6.5.5 GPIOR2 – General Purpose I/O Register 2
6.5.6 GPIOR1 – General Purpose I/O Register 1
6.5.7 GPIOR0 – General Purpose I/O Register 0
Bit 76543210
0x15 (0x35) MSB LSB GPIOR2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x14 (0x34) MSB LSB GPIOR1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x13 (0x33) MSB LSB GPIOR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0