Datasheet

7701F–AVR–10/12

Atmel ATtiny24/44/84 [Preliminary]

• Bit 7 – Res: Reserved Bit

This bit is reserved for future use, and will always read as 0 in Atmel

ATtiny24/44/84. For

compatibility with future AVR

devices, always write this bit to a logical zero. After reading,

mask out this bit.

• Bit 6 – Res: Reserved Bit

This bit is reserved in the Atmel ATtiny24/44/84 and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Mode Bits

The EEPROM programming mode bits define which programming action will be triggered

when writing EEPE. It is possible to program data in one atomic operation (erase the old value

and program the new value) or split the erase and write operations into two separate opera-

tions. The programming times for the different modes are shown in Table 6-1. While EEPE is

set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00

unless the EEPROM is busy programming.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to logical one enables the EEPROM ready interrupt if the I-bit in SREG is set.

Writing EERIE to logical zero disables the interrupt. The EEPROM ready interrupt generates a

constant interrupt when non-volatile memory is ready for programming.

• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to logical one will have effect or not. When

EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected

address. If EEMPE is logical zero, setting EEPE will have no effect. When EEMPE has been

written to logical one by software, hardware clears the bit to logical zero after four clock cycles.

• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM program enable bit, EEPE, is the programming enable signal to the EEPROM.

When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting.

The EEMPE bit must be written to logical one before a logical one is written to EEPE, other-

wise no EEPROM write will take place. When the write access time has elapsed, the EEPE bit

is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the

next instruction is executed.

Table 6-1. EEPROM Mode Bits

EEPM1 EEPM0

Programming

Time Operation

0 0 3.4ms Erase and Write in one operation (Atomic Operation)

0 1 1.8ms Erase Only

1 0 1.8ms Write Only

1 1 – Reserved for future use