Datasheet

168
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
21.6.1 Serial Programming Algorithm
When writing serial data to the Atmel
®
AVR
®
ATtiny24/44/84, data are clocked on the rising
edge of SCK.
When reading data from the Atmel ATtiny24/44/84, data are clocked on the falling edge of
SCK. See Figure 22-3 and Figure 22-4 for timing details.
To program and verify the Atmel ATtiny24/44/84 in the serial programming mode, the following
sequence is recommended (see four-byte instruction formats in Table 21-11):
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET
must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of syn-
chronization. When in sync, the second byte (0x53) will echo back when issuing the
third byte of the programming enable instruction. Regardless of whether the echo is
correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not
echo back, give RESET
a positive pulse and issue a new programming enable
command.
4. The flash is programmed one page at a time. The memory page is loaded one byte at
a time by supplying the five LSBs of the address and data together with the load pro-
gram memory page instruction. To ensure correct loading of the page, the data low
byte must be loaded before the data high byte is applied for a given address. The pro-
gram memory page is stored by loading the write program memory page instruction
with the three MSBs of the address. If polling (RDY/BSY
) is not used, the user must
wait at least tWD_FLASH before issuing the next page. (See Table 21-10 on page
169.) Accessing the serial programming interface before the Flash write operation
completes can result in incorrect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data are written. If polling (RDY/BSY)
is not used,
the user must wait at least t
WD_EEPROM
before issuing the next byte. (See Table 21-10
on page 169.) In a chip erased device, no 0xFFs in the data file(s) need to be pro-
grammed.
B: The EEPROM array is programmed one page at a time. The Memory page is
loaded one byte at a time by supplying the two LSBs of the address and data together
with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is
stored by loading the Write EEPROM Memory Page Instruction with the four MSBs of
the address. When using EEPROM page access only byte locations loaded with the
Load EEPROM Memory Page instruction is altered. The remaining locations remain
unchanged. If polling (RDY/BSY)
is not used, the used must wait at least t
WD_EEPROM
before issuing the next page (See Table 21-10 on page 169). In a chip-erased device,
no 0xFF in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the
content at the selected address at serial output MISO.
7. At the end of the programming session, RESET
can be set high to commence normal
operation.