Datasheet

167
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
21.6 Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus
while RESET
is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and
MISO (output). After RESET
is set low, the Programming Enable instruction needs to be exe-
cuted first before program/erase operations can be executed. NOTE, in Table 21-9 on page
167, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated
for the internal SPI interface.
Figure 21-1. Serial Programming and Verify
(1)
Note: 1. If the device is clocked by the internal oscillator, it is not needed to connect a clock source to
the CLKI pin.
When programming the EEPROM, an auto-erase cycle is built into the self-timed program-
ming operation (in serial mode only), and there is no need to first execute the chip erase
instruction. The chip erase operation turns the content of every memory location in both the
program and EEPROM arrays into 0xFF.
Depending on the CKSEL fuses, a valid clock must be present. The minimum low and high
periods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
>= 12MHz
High: > 2 CPU clock cycles for f
ck
< 12MHz, 3 CPU clock cycles for f
ck
>= 12MHz
Table 21-9. Pin Mapping Serial Programming
Symbol Pins I/O Description
MOSI PA6 I Serial Data in
MISO PA5 O Serial Data out
SCK PA4 I Serial Clock
VCC
GND
SCK
MISO
MOSI
RESET
+1.8 - 5.5V