Datasheet

161
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
Flash corruption can easily be avoided by following at least one these design
recommendations:
1. Keep the Atmel
®
AVR
®
RESET active (low) during periods of insufficient power supply
voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the
operating voltage matches the detection level. If not, an external low V
CC
reset protec-
tion circuit can be used. If a reset occurs while a write operation is in progress, the
write operation will be completed provided the power supply voltage is sufficient.
2. Keep the AVR core in power-down sleep mode during periods of low VCC. This will
prevent the CPU from attempting to decode and execute instructions, effectively pro-
tecting SPMCSR and, thus, the flash from unintentional writes.
20.4.4 Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 20-1 shows the typical pro-
gramming time for Flash accesses from the CPU.
Note: 1. The min and max programming times are per individual operation.
20.5 Register Description
20.5.1 SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to
control Program memory operations.
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny24/44/84 and always read as zero.
• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will
be cleared and the data will be lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SPMEN are set in SPMCSR will read
either the lock bits or the fuse bits (depending on Z0 in the Z-pointer) in the destination regis-
ter. See “EEPROM Write Prevents Writing to SPMCSR” on page 160 for details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four
clock cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer.
Table 20-1. SPM Programming Time
(1)
Symbol Min Programming Time Max Programming Time
Flash write (Page Erase, Page Write,
and write Lock bits by SPM)
3.7 ms 4.5 ms
Bit 7 6 5 4 3 2 1 0
0x37 (0x57)
– – – CTPB RFLB PGWRT PGERS SPMEN SPMCSR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0