Datasheet

16
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and 128/256/512 bytes of internal
data SRAM in the Atmel
®
ATtiny24/44/84 are all accessible through all these addressing
modes. The Register File is described in “General Purpose Register File” on page 10.
Figure 6-2. Data Memory Map
6.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU
cycles as described in Figure 6-3 on
page 16.
Figure 6-3. On-chip Data SRAM Access Cycles
32 Registers
64 I/O Registers
Internal SRAM
(128/256/512 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x0DF/0x015F/0x025F
0x0060
Data Memory
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction