Datasheet

153
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
18.10.3 ADCL and ADCH – ADC Data Register
18.10.3.1 ADLAR = 0
18.10.3.2 ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently,
if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADCSRB, and the MUXn bits in ADMUX affect the way the result is read
from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the
result is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result”
on page 147.
100 16
101 32
110 64
111 128
Table 18-6. ADC Prescaler Selections (Continued)
ADPS2 ADPS1 ADPS0 Division Factor
Bit 151413121110 9 8
0x05 (0x25) ––––––ADC9ADC8ADCH
0x04 (0x24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
76543210
Read/WriteRRRRRRRR
RRRRRRRR
Initial Value00000000
00000000
Bit 151413121110 9 8
0x05 (0x25) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
0x04 (0x24) ADC1 ADC0 – – – – – – ADCL
76543210
Read/WriteRRRRRRRR
RRRRRRRR
Initial Value00000000
00000000