Datasheet

143
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
18.6 Changing Channel or Reference Selection
The MUX5:0 and REFS1:0 bits in the ADMUX register are single-buffered through a tempo-
rary register to which the CPU has random access. This ensures that the channel and
reference selection only takes place at a safe point during the conversion. The channel and
reference selection is continuously updated until a conversion is started. Once the conversion
starts, the channel and reference selection is locked to ensure a sufficient sampling time for
the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion
completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising
ADC clock edge after ADSC is written. The user is thus advised not to write new channel or
reference selection values to ADMUX until one ADC clock cycle after ADSC is written.
If auto triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX register in order to control which conversion
will be affected by the new setting.
If both ADATE and ADEN are written to logical one, an interrupt event can occur at any time. If
the ADMUX register is changed in this period, the user cannot tell if the next conversion is
based on the old or the new setting. The ADMUX register can be safely updated in the follow-
ing ways:
a. When ADATE or ADEN is cleared.
b. During conversion, minimum one ADC clock cycle after the trigger event.
c. After a conversion, before the Interrupt Flag used as the trigger source is cleared.
When updating the ADMUX register in one of these conditions, the new setting will affect the
next ADC conversion.
18.6.1 ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
In single-conversion mode, always select the channel before starting the conversion. The
channel selection may be changed one ADC clock cycle after writing logical one to ADSC.
However, the simplest method is to wait for the conversion to complete before changing the
channel selection.
In free running mode, always select the channel before starting the first conversion. The chan-
nel selection may be changed one ADC clock cycle after writing logical one to ADSC.
However, the simplest method is to wait for the first conversion to complete, and then change
the channel selection. Because the next conversion has already started automatically, the
next result will reflect the previous channel selection. Subsequent conversions will reflect the
new channel selection.
18.6.2 ADC Voltage Reference
The reference voltage for the ADC (V
REF
) indicates the conversion range for the ADC. Sin-
gle-ended channels that exceed V
REF
will result in codes close to 0x3FF. V
REF
can be selected
as either V
CC
, internal 1.1V reference, or external AREF pin. The first ADC conversion result
after switching the reference voltage source may be inaccurate, and the user is advised to dis-
card this result.