Datasheet

142
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
Figure 18-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 18-7. ADC Timing Diagram, Free Running Conversion
Table 18-1. ADC Conversion Time
Condition
Sample-and-Hold (Cycles
from Start of Conversion) Conversion Time (Cycles)
First conversion 14.5 25
Normal conversions 1.5 13
Auto Triggered conversions 2 13.5
1 2 3 4 5 6 7 8
9
10 11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update
11 12 13
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
12
One Conversion Next Conversion
34
Conversion
Complete
Sample & Hold
MUX and REFS
Update