Datasheet

140
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
Figure 18-2. ADC Auto Trigger Logic
Using the ADC interrupt flag as a trigger source makes the ADC start a new conversion as
soon as the ongoing conversion has finished. The ADC then operates in free running mode,
constantly sampling and updating the ADC data register. The first conversion must be started
by writing a logical one to the ADSC bit in ADCSRA. In this mode, the ADC will perform suc-
cessive conversions independently of whether the ADC interrupt flag (ADIF) is cleared or not.
If auto triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
logical one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit
will be read as logical one during a conversion independently of how the conversion was
started.
18.5 Prescaling and Conversion Timing
Figure 18-3. ADC Prescaler
By default, the successive approximation circuitry requires an input clock frequency between
50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.The
ADC module contains a prescaler, which generates an acceptable ADC clock frequency from
any CPU frequency above 100kHz.
ADSC
ADIF
SOURCE 1
SOURCE n
ADTS[2:0]
CONVERSION
LOGIC
PRESCALER
START
CLK
ADC
.
.
.
.
EDGE
DETECTOR
ADATE
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2 CK/4 CK/8
CK/16
CK/32
CK/64
Reset
ADEN
START