Datasheet

136
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, ACI is cleared by writing a logical one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logical one and the I-bit in the status register is set, the analog
comparator interrupt is activated. When written logical zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logical one, this bit enables the input capture function in timer/counter 1 to be
triggered by the analog comparator. The comparator output is in this case directly connected
to the input capture front-end logic, making the comparator utilize the noise canceller and
edge select features of the timer/counter 1 input capture interrupt. When written logical zero,
no connection between the analog comparator and the input capture function exists. To make
the comparator trigger the timer/counter 1 input capture interrupt, the ICIE1 bit in the timer
interrupt mask register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events trigger the analog comparator interrupt. The
different settings are shown in Table 17-2.
When changing the ACIS1/ACIS0 bits, the analog comparator interrupt must be disabled by
clearing its interrupt enable bit in the ACSR. Otherwise, an interrupt can occur when the bits
are changed.
17.2.3 DIDR0 – Digital Input Disable Register 0
• Bits 1, 0 – ADC0D,ADC1D: ADC 1/0 Digital input buffer disable
When this bit is written logical one, the digital input buffer on the AIN1/0 pin is disabled. The
corresponding PIN register bit will always read as zero when this bit is set. When an analog
signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit
should be written logical one to reduce power consumption in the digital input buffer.
Table 17-2. ACIS1/ACIS0 Settings
ACIS1 ACIS0 Interrupt Mode
0 0 Comparator Interrupt on Output Toggle.
01Reserved
1 0 Comparator Interrupt on Falling Output Edge.
1 1 Comparator Interrupt on Rising Output Edge.
Bit 76543210
0x01 (0x21)
ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000