Datasheet

127
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
16.3.4 Two-wire Mode
The USI two-wire mode is compliant with the Inter-IC (I2C or TWI) bus protocol, but without
slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL
and SDA.
Figure 16-4. Two-wire Mode Operation, Simplified Diagram
Figure 16-4 on page 127 shows two USI units operating in two-wire mode, one as master and
one as slave. Only the physical layer is shown because the system operation is highly depen-
dent of the communication scheme used. The main differences between the master and slave
operation at this level are that the serial clock generation is always done by the master, and
only the slave uses the clock control unit. Clock generation must be implemented in software,
but the shift operation is done automatically by both devices. Note that only clocking on the
negative edge to shift data is practical in this mode. The slave can insert wait states at the start
or end of a transfer by forcing the SCL clock low. This means that the master must always
check if the SCL line was actually released after it has generated a positive edge.
Because the clock also increments the counter, a counter overflow can be used to indicate
that the transfer has completed. The master generates clock by the by toggling the USCK pin
via the PORT register.
The data direction is not given by the physical layer. A protocol, like the one used by the
TWI-bus, must be implemented to control the data flow.
MASTER
SLAVE
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SDA
SCL
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Two-wire Clock
Control Unit
HOLD
SCL
PORTxn
SDA
SCL
VCC