Datasheet

123
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
The 4-bit counter can be both read and written via the data bus, and can generate an overflow
interrupt. Both the serial register and the counter are clocked simultaneously by the same
clock source. This allows the counter to count the number of bits received or transmitted and
generate an interrupt when the transfer is complete. Note that when an external clock source
is selected, the counter counts both clock edges. In this case, the counter counts the number
of edges, and not the number of bits. The clock can be selected from three different sources:
the USCK pin, timer/counter 0 compare match, or from software.
The two-wire clock control unit can generate an interrupt when a start condition is detected on
the two-wire bus. It can also generate wait states by holding the clock pin low after a start con-
dition is detected, or after the counter overflows.
16.3 Functional Descriptions
16.3.1 Three-wire Mode
The USI three-wire mode is compliant with the serial peripheral interface (SPI) mode 0 and 1,
but does not have the slave select (SS) pin functionality. However, this feature can be imple-
mented in software if necessary. Pin names used by this mode are: DI, DO, and USCK.
Figure 16-2. Three-wire Mode Operation, Simplified Diagram
Figure 16-2 on page 123 shows two USI units operating in three-wire mode, one as master
and one as slave. The two shift registers are interconnected in such way that after eight USCK
clocks, the data in each register are interchanged. The same clock also increments the USI's
4-bit counter. The counter overflow (interrupt) flag, or USIOIF, can therefore be used to deter-
mine when a transfer is completed. The clock is generated by the master device software by
toggling the USCK pin via the PORT register, or by writing a logical one to the USITC bit in
USICR.
SLAVE
MASTER
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DO
DI
USCK
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DO
DI
USCK
PORTxn