Datasheet

121
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the
system clock frequency (f
ExtClk
< f
clk_I/O
/2) given a 50/50 duty cycle. Because the edge detector
uses sampling, the maximum frequency of an external clock it can detect is half the sampling
frequency (Nyquist sampling theorem). However, due to variation of the system clock fre-
quency and duty cycle caused by oscillator source (crystal, resonator, and capacitor)
tolerances, it is recommended that the maximum frequency of an external clock source is less
than f
clk_I/O
/2.5.
An external clock source can not be prescaled.
Figure 15-2. Prescaler for Timer/Counter0
Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 15-1 on page 120.
15.3 Register Description
15.3.1 GTCCR – General Timer/Counter Control Register
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to logical one activates the timer/counter synchronization mode. In this
mode, the value that is written to the PSR10 bit is kept, hence keeping the prescaler reset sig-
nal asserted. This ensures that the timer/counter is halted and can be configured without the
risk of advancing during configuration. When the TSM bit is written to logical zero, the PSR10
bit is cleared by hardware, and the timer/counter starts counting.
• Bit 0 – PSR10: Prescaler 0 Reset Timer/Counter n
When this bit is set to one, the timer/counter n prescaler will be reset. This bit is normally
cleared immediately by hardware, except if the TSM bit is set.
PSR10
Clear
clk
T0
T0
clk
I/O
Synchronization
Bit 7 6 5 4 3 2 1 0
0x23 (0x43) TSM
– – – – – – PSR10 GTCCR
Read/Write R/W R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0