Datasheet

111
7701F–AVR–10/12
Atmel ATtiny24/44/84 [Preliminary]
Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 14-11 on page 111 shows the same timing data, but with the prescaler enabled.
Figure 14-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
clk_I/O
/8)
Figure 14-12 on page 112 shows the count sequence close to TOP in various modes. When
using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM.
The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by
BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at
BOTTOM.
clk
Tn
(clk
I/O
/1)
OCFnx
clk
I/O
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)