Features • High Performance, Low Power AVR 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 2/4/8K Byte of In-System Programmable Program Memory Flash (AtmelATtiny24/44/84) Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes In-System Programmable EEPROM (Atmel ATtiny24/44/84) Endurance: 100,000 Write/Erase Cy
1. Pin Configurations Figure 1-1. Pinout Atmel® ATtiny24/44/84 SOIC VCC (PCINT8/XTAL1) PB0 (PCINT9/XTAL2) PB1 (PCINT11/RESET/dW) PB3 (PCINT10/INT0/OC0A/CKOUT) PB2 (PCINT7/ICP/OC0B/ADC7) PA7 (PCINT6/OC1A/SDA/MOSI/ADC6) PA6 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND PA0 (ADC0/AREF/PCINT0) PA1 (ADC1/AIN0/PCINT1) PA2 (ADC2/AIN1/PCINT2) PA3 (ADC3/T0/PCINT3) PA4 (ADC4/USCK/SCL/T1/PCINT4) PA5 (ADC5/DO/MISO/OC1B/PCINT5) NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect 1.
Atmel ATtiny24/44/84 [Preliminary] 2. Overview The Atmel® ATtiny24/44/84 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel ATtiny24/44/84 achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1.
The Atmel® AVR® core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
Atmel ATtiny24/44/84 [Preliminary] 2.3 2.3.1 Pin Descriptions VCC Supply voltage. 2.3.2 GND Ground. 2.3.3 Port B (PB3...PB0) Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3, which has the RESET capability. To use pin PB3 as an I/O pin instead of RESET pin, program (‘0’) RSTDISBL fuse.
3. Resources A comprehensive set of development tools, driver and application notes, and datasheets are available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part-specific header file is included before compilation.
Atmel ATtiny24/44/84 [Preliminary] 5. CPU Core 5.1 Overview This section discusses the Atmel® AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must, therefore, be able to access memories, perform calculations, control peripherals, and handle interrupts. 5.2 Architectural Overview Figure 5-1.
The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle arithmetic logic unit (ALU) operation. In a typical ALU operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file, all in one clock cycle.
Atmel ATtiny24/44/84 [Preliminary] The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 5.4.1 SREG – AVR Status Register Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set for the interrupts to be enabled.
5.5 General Purpose Register File The register file is optimized for the Atmel® AVR® Enhanced RISC instruction set.
Atmel ATtiny24/44/84 [Preliminary] Figure 5-3. The X-, Y-, and Z-registers 15 XH XL 7 X-register 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes, these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set summary for details). 5.
5.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The Atmel® AVR® CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 5-4 on page 12 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access register file concept.
Atmel ATtiny24/44/84 [Preliminary] When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The user software can write a logical one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a return from interrupt instruction, RETI, is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 5.8.
Atmel ATtiny24/44/84 [Preliminary] 6. Memories This section describes the different memories in the Atmel® ATtiny24/44/84. The AVR® architecture has two main memory spaces, the data memory space and the program memory space. In addition, the Atmel ATtiny24/44/84 features an EEPROM memory for data storage. All three memory spaces are linear and regular. 6.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and 128/256/512 bytes of internal data SRAM in the Atmel® ATtiny24/44/84 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10. Figure 6-2.
Atmel ATtiny24/44/84 [Preliminary] 6.3 EEPROM Data Memory The Atmel® ATtiny24/44/84 contains 128/256/512 bytes of EEPROM data memory. It is organized as a separate data space in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following sections specifying the EEPROM address registers, the EEPROM data register, and the EEPROM control register.
6.3.4 Erase To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Table 1). The EEPE bit remains set until the erase operation completes. While the device is busy programming, it is not possible to do any other EEPROM operations. 6.3.5 Write To write a location, the user must write the address into EEAR and the data into EEDR.
Atmel ATtiny24/44/84 [Preliminary] Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set Programming mode ldi r16, (0<
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
Atmel ATtiny24/44/84 [Preliminary] 6.4 I/O Memory The I/O space definition of the Atmel® ATtiny24/44/84 is shown in “Register Summary” on page 210. All Atmel ATtiny24/44/84 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
6.5 6.5.1 Register Description EEARH – EEPROM Address Register Bit 7 6 5 4 3 2 1 0 0x1F (0x3F) – – – – – – – EEAR8 Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 X EEARH • Bits 7..1 – Res: Reserved Bits These are reserved bits in the ATtiny24/44/84, and will always read as zero. • Bit 0 – EEAR8: EEPROM Address The EEPROM address register, EEARH, specifies the most-significant bit for EEPROM address in the 512-byte EEPROM space for Tiny84.
Atmel ATtiny24/44/84 [Preliminary] • Bit 7 – Res: Reserved Bit This bit is reserved for future use, and will always read as 0 in Atmel® ATtiny24/44/84. For compatibility with future AVR® devices, always write this bit to a logical zero. After reading, mask out this bit. • Bit 6 – Res: Reserved Bit This bit is reserved in the Atmel ATtiny24/44/84 and will always read as zero.
• Bit 0 – EERE: EEPROM Read Enable The EEPROM read enable signal, EERE, is the read strobe for the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to logical one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data are available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation.
Atmel ATtiny24/44/84 [Preliminary] 7. System Clock and Clock Options 7.1 Clock Systems and their Distribution Figure 7-1 on page 25 presents the principal clock systems in the AVR® and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 34. The clock systems are detailed below. Figure 7-1.
7.1.4 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by their digital circuitry. This gives more accurate ADC conversion results. 7.2 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the Atmel® AVR® clock generator, and routed to the appropriate modules.
Atmel ATtiny24/44/84 [Preliminary] 7.4 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 7-2. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment.
Table 7-4. CKSEL0 SUT1..0 Start-up Time from Power-down and Power-save 0 00 258 CK(1) 14CK + 4.1ms Ceramic resonator, fast rising power 0 01 258 CK(1) 14CK + 65ms Ceramic resonator, slowly rising power 0 10 1K CK(2) 14CK Ceramic resonator, BOD enabled 0 11 1K CK(2) 14CK + 4.1ms Ceramic resonator, fast rising power 1 00 1K CK(2) 14CK + 65ms Ceramic resonator, slowly rising power 1 01 16K CK 14CK Crystal Oscillator, BOD enabled 1 10 16K CK 14CK + 4.
Atmel ATtiny24/44/84 [Preliminary] 7.6 Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 22-2 on page 180 and “Internal Oscillator Speed” on page 204 for more details. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 31 for more details.
Figure 7-3. External Clock Drive Configuration EXTERNAL CLOCK SIGNAL CLKI GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 7-8 on page 30. Table 7-8. Start-up Times for the External Clock Selection SUT1..
Atmel ATtiny24/44/84 [Preliminary] 7.8 128kHz Internal Oscillator The 128kHz internal oscillator is a low power oscillator providing a 128kHz clock. The frequency is nominal at 3V and 25°C. This clock may be selected as the system clock by programming the CKSEL fuses to "0100". When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 7-9 on page 31. Table 7-9. SUT1..
7.10 7.10.1 Register Description Oscillator Calibration Register – OSCCAL Bit 7 6 5 4 3 2 1 0 0x31 (0x51) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
Atmel ATtiny24/44/84 [Preliminary] To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
8. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The Atmel® AVR® provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 8.1 Sleep Modes Figure 7-1 on page 25 presents the different clock systems in the Atmel® ATtiny24/44/84, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
Atmel ATtiny24/44/84 [Preliminary] Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 8.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60µs to ensure that the BOD is working correctly before the MCU continues executing code. BOD disable is controlled by the BODS (BOD Sleep) bit of MCU Control Register, see Section 8.9.1 “MCUCR – MCU Control Register” on page 38. Writing this bit to one turns off BOD in Power-Down and Stand-By, while writing a zero keeps the BOD active. The default setting is zero, i.e. BOD active.
Atmel ATtiny24/44/84 [Preliminary] 8.8.3 Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. See “Brown-out Detection” on page 43 for details on how to configure the Brown-out Detector. 8.8.
8.9 8.9.1 Register Description MCUCR – MCU Control Register The MCU Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 7 – BODS: BOD Sleep In order to disable BOD during sleep (see Table 8-1 on page 34) the BODS bit must be written to logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR.
Atmel ATtiny24/44/84 [Preliminary] 8.9.2 PRR – Power Reduction Register Bit 7 6 5 4 3 2 1 0 – – – – PRTIM1 PRTIM0 PRUSI PRADC Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PRR • Bits 7, 6, 5, 4- Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bit 3- PRTIM1: Power Reduction Timer/Counter1 Writing a logical one to this bit shuts down the timer/counter 1 module.
9. System Control and Reset 9.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 9-1 on page 41 shows the reset logic.
Atmel ATtiny24/44/84 [Preliminary] Figure 9-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [1..0] Pull-up Resistor SPIKE FILTER Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[1:0] SUT[1:0] 9.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in “System and Reset Characterizations” on page 181.
Figure 9-3. MCU Start-up, RESET Extended Externally VPOT VCC VRST RESET tTOUT TIME-OUT INTERNAL RESET Table 9-1. Symbol Power On Reset Specifications Parameter Power-on Reset Threshold Voltage (rising) VPOT Typ Max Unit 1.1 1.4 1.7 V 0.8 1.3 1.6 V 0.4 V VPORMAX VCC Max. start voltage to ensure internal Power-on Reset signal VPORMIN VCC Min. start voltage to ensure internal Power-on Reset signal -0.1 V VCCRR VCC Rise Rate to ensure Power-on Reset 0.
Atmel ATtiny24/44/84 [Preliminary] Figure 9-4. External Reset During Operation CC 9.5 Brown-out Detection ATtiny24/44/84 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection.
Figure 9-6. Watchdog Reset During Operation CC CK 9.7 Internal Voltage Reference The Atmel® ATtiny24/44/84 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 9.7.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in “System and Reset Characterizations” on page 181.
Atmel ATtiny24/44/84 [Preliminary] To prevent unintentional disabling of the watchdog or unintentional change of time-out period, two different safety levels are selected by the WDTON fuse, as shown in Table 9-2. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45 for details. Table 9-2.
9.10 9.10.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 7 6 5 4 3 2 1 0 0x34 (0x54) – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
Atmel ATtiny24/44/84 [Preliminary] If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared, the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 9-3.
Table 9-4. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 0 0 0 0 2K cycles 16ms 0 0 0 1 4K cycles 32ms 0 0 1 0 8K cycles 64ms 0 0 1 1 16K cycles 0.125s 0 1 0 0 32K cycles 0.25s 0 1 0 1 64K cycles 0.5s 0 1 1 0 128K cycles 1.0s 0 1 1 1 256K cycles 2.0s 1 0 0 0 512K cycles 4.0s 1 0 0 1 1024K cycles 8.
Atmel ATtiny24/44/84 [Preliminary] The following code example shows one assembly function and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
10. Interrupts This section describes the specifics of the interrupt handling as performed in Atmel ® ATtiny24/44/84. For a general explanation of the AVR® interrupt handling, see “Reset and Interrupt Handling” on page 12. 10.1 Interrupt Vectors Table 10-1. 50 Reset and Interrupt Vectors Vector No.
Atmel ATtiny24/44/84 [Preliminary] If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
11. External Interrupts The external interrupts are triggered by the INT0 pin or any of the PCINT11..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT11..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change 0 interrupts (PCI0) will trigger if any enabled PCINT7..0 pin toggles. Pin change 1 interrupts (PCI1) will trigger if any enabled PCINT11..8 pin toggles.
Atmel ATtiny24/44/84 [Preliminary] 11.2 11.2.1 Register Description MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 4– PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set and the I-bit in the Status Register (SREG) is set, pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of pin change interrupt request is executed from the PCI0 interrupt vector. PCINT7..0 pins are enabled individually by the PCMSK0 register. 11.2.
Atmel ATtiny24/44/84 [Preliminary] • Bits 3..0 – PCINT11..8: Pin Change Enable Mask 11..8 Each PCINT11..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT11..8 is set (logical one) and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT11..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 11.2.
12. I/O Ports 12.1 Overview All Atmel® AVR® ports have true read-modify-write functionality when used as general digital I/O ports. This means that the SBI and CBI instructions can be used to change direction of one port pin without unintentionally changing the direction of any other pin. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Atmel ATtiny24/44/84 [Preliminary] Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 12.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 12-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 12-2.
If PORTxn is written logical one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logical zero when the pin is configured as an output pin, the port pin is driven low (zero). 12.2.2 Toggling the Pin Writing a logical one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 12.2.
Atmel ATtiny24/44/84 [Preliminary] Figure 12-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal.
The following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
Atmel ATtiny24/44/84 [Preliminary] If a logic high level (logical one) is present on an asynchronous external interrupt pin configured as "interrupt on rising edge, falling edge, or any logic change on pin" while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep mode, as the clamping in these sleep mode produces the requested logic change. 12.2.
Figure 12-5.
Atmel ATtiny24/44/84 [Preliminary] Table 12-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.
12.3.1 Alternate Functions of Port A The Port A pins with alternate function are shown in Table 12-7 on page 68. Table 12-3. Port A Pins Alternate Functions Port Pin Alternate Function PA0 ADC0: ADC input channel 0. AREF: External analog reference. PCINT0: Pin change interrupt 0 source 0. PA1 ADC1: ADC input channel 1. AIN0: Analog Comparator Positive Input. PCINT1:Pin change interrupt 0 source 1. PA2 ADC2: ADC input channel 2. AIN1: Analog Comparator Negative Input.
Atmel ATtiny24/44/84 [Preliminary] • Port A, Bit 1 – ADC1/AIN0/PCINT1 ADC1: Analog to Digital Converter, Channel 1. AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCINT1: Pin Change Interrupt source 1. The PA1 pin can serve as an external interrupt source for pin change interrupt 0.
• Port A, Bit 6 – ADC6/DI/SDA/OC1A/PCINT6 ADC6: Analog to Digital Converter, Channel 6. SDA: Two-wire mode Serial Interface Data. DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function. OC1A: Output compare match output: The PA6 pin can serve as an external output for the Timer/Counter1 compare match A. The PA6 pin has to be configured as an output (DDA6 set (one)) to serve this function.
Atmel ATtiny24/44/84 [Preliminary] Table 12-5. Overriding Signals for Alternate Functions in PA4..
12.3.2 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 12-7 on page 68. Table 12-7. Port B Pins Alternate Functions Port Pin Alternate Function PB0 XTAL1: Crystal Oscillator Input. PCINT8: Pin change interrupt 1 source 8. PB1 XTAL2: Crystal Oscillator Output. PCINT9: Pin change interrupt 1 source 9. PB2 INT0: External Interrupt 0 Input. OC0A: Timer/Counter0 Compare Match A output. CKOUT: System clock output. PCINT10:Pin change interrupt 1 source 10.
Atmel ATtiny24/44/84 [Preliminary] • Port B, Bit 3 – RESET/dW/PCINT11 RESET: External Reset input is active low and enabled by un-programming ("1") the RSTDISBL fuse. Pull-up is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. dW: When the debugWIRE enable (DWEN) fuse is programmed and lock bits are un-programmed, the debugWIRE system within the target device is activated.
Table 12-9. Signal Name Overriding Signals for Alternate Functions in PB1..PB0 PB1/XTAL2/PCINT9 PB0/XTAL1/PCINT8 (1) EXT_CLOCK (2) + EXT_OSC(1) PUOE EXT_OSC PUOV 0 0 DDOE EXT_OSC(1) EXT_CLOCK(2) + EXT_OSC(1) DDOV 0 0 PVOE EXT_OSC PVOV 0 PTOE 0 (1) EXT_CLOCK(2) + EXT_OSC(1) 0 0 (1) 12.4 12.4.
Atmel ATtiny24/44/84 [Preliminary] 12.4.3 DDRA – Port A Data Direction Register Bit 12.4.4 7 6 5 4 3 2 1 0 0x1A (0x3A) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PINA – Port A Input Pins Address Bit 12.4.5 12.4.6 12.4.
13. 8-bit Timer/Counter0 with PWM 13.1 Features • • • • • • • 13.2 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/counter 0 is a general purpose 8-bit timer/counter module, with two independent output compare units, and with PWM support.
Atmel ATtiny24/44/84 [Preliminary] Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B).
Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
Atmel ATtiny24/44/84 [Preliminary] Figure 13-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x registers are double buffered when using any of the pulse width modulation (PWM) modes. For the normal and clear timer on compare (CTC) modes of operation, the double buffering is disabled.
13.5.3 Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved in changing TCNT0 when using the output compare unit, independently of whether the timer/counter is running or not. If the value written to TCNT0 equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to bottom when the counter is down-counting.
Atmel ATtiny24/44/84 [Preliminary] The design of the output compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation, see “Register Description” on page 84 13.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.
The timing diagram for the CTC mode is shown in Figure 13-5 on page 78. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 13-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the top value by using the OCF0A flag.
Atmel ATtiny24/44/84 [Preliminary] This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows the use of physically smaller external components (coils, capacitors, etc.), and hence reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle.
The extreme values for the OCR0A register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to bottom, the out- put will be a narrow spike for each max+1 timer clock cycle. Setting the OCR0A equal to max will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits).
Atmel ATtiny24/44/84 [Preliminary] Figure 13-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 The timer/counter overflow flag (TOV0) is set each time the counter reaches bottom. The interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
• OCR0A changes its value from MAX, as in Figure 13-7 on page 81. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the compare match and, hence, the OCn change that would have happened on the way up. 13.
Atmel ATtiny24/44/84 [Preliminary] Figure 13-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 13-11 on page 83 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. Figure 13-11.
13.9 13.9.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x30 (0x50) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the output compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to.
Atmel ATtiny24/44/84 [Preliminary] Table 13-4 on page 85 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 13-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting.
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 78 for more details. Table 13-4 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 13-7. COM0A1 COM0A0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting.
Atmel ATtiny24/44/84 [Preliminary] 13.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x33 (0x53) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
Table 13-9. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
Atmel ATtiny24/44/84 [Preliminary] 13.9.6 TIMSK0 – Timer/Counter 0 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 0x39 (0x59) – – – – – OCIE0B OCIE0A TOIE0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK0 • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny24/44/84 and will always read as zero.
• Bit 0– TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in timer/counter 0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical one to the flag. When the SREG I-bit, TOIE0 (timer/counter 0 overflow interrupt enable), and TOV0 are set, the timer/counter 0 overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting.
Atmel ATtiny24/44/84 [Preliminary] 14. 16-bit Timer/Counter1 14.1 Features • • • • • • • • • • • 14.2 True 16-bit Design (i.e.
Figure 14-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 14.2.1 TCCRnB 1.
Atmel ATtiny24/44/84 [Preliminary] The double buffered output compare registers (OCR1A/B) are compared with the timer/counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the output compare pin (OC1A/B). See “Output Compare Units” on page 100. The compare match event will also set the compare match flag (OCF1A/B) which can be used to generate an output compare interrupt request.
14.3 Accessing 16-bit Registers TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the Atmel® AVR® CPU via the 8-bit data bus. The 16-bit registers must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storage of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation.
Atmel ATtiny24/44/84 [Preliminary] It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register and the interrupt code updates the temporary register by accessing the same or any of the other 16-bit timer registers, then the result of the access outside the interrupt will be corrupted.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Atmel ATtiny24/44/84 [Preliminary] 14.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 14-2 on page 97 shows a block diagram of the counter and its surroundings. Figure 14-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 14.6 Input Capture Unit The timer/counter incorporates an input capture unit that can capture external events and give them a time stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or, alternatively, via the analog comparator unit.
Atmel ATtiny24/44/84 [Preliminary] The ICR1 register can only be written when using a waveform generation mode that utilizes the ICR1 register for defining the counter's top value. In these cases the waveform generation mode (WGM13:0) bits must be set before the top value can be written to the ICR1 register. When writing the ICR1 register, the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L.
Measurement of an external signal's duty cycle requires that the trigger edge be changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 register has been read. After a change of the edge, the input capture flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 flag is not required (if an interrupt handler is used). 14.
Atmel ATtiny24/44/84 [Preliminary] The OCR1x register is double buffered when using any of the twelve pulse width modulation (PWM) modes. For the normal and clear timer on compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x compare register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 14.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source.
Atmel ATtiny24/44/84 [Preliminary] 14.8.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the OC1x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 14-1 on page 113.
The timing diagram for the CTC mode is shown in Figure 14-6 on page 104. The counter value (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 14-6.
Atmel ATtiny24/44/84 [Preliminary] In non-inverting compare output mode, the output compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x, and set at bottom. In inverting compare output mode, output is set on compare match and cleared at bottom. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation.
When changing the top value, the program must ensure that the new top value is higher or equal to the value of all of the compare registers. If the top value is lower than any of the compare registers, a compare match will never occur between TCNT1 and OCR1x. Note that when using fixed top values, the unused bits are masked to zero when any of the OCR1x Registers are written The procedure for updating ICR1 differs from that for updating OCR1A when used for defining the top value.
Atmel ATtiny24/44/84 [Preliminary] 14.9.4 Phase Correct PWM Mode The phase correct pulse width modulation, or phase correct PWM, mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high-resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from bottom (0x0000) to top and then from top to bottom.
The timer/counter overflow flag (TOV1) is set each time the counter reaches bottom. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag is set accordingly on the same timer clock cycle on which the OCR1x registers are updated with the double buffer value (at top). The interrupt flags can be used to generate an interrupt each time the counter reaches the top or bottom value.
Atmel ATtiny24/44/84 [Preliminary] In inverting compare output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications.
When changing the top value, the program must ensure that the new top value is higher or equal to the value of all of the compare registers. If the top value is lower than any of the compare registers, a compare match will never occur between TCNT1 and OCR1x. As Figure 14-9 on page 109 shows, the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCR1x registers are updated at bottom, the length of the rising and the falling slopes will always be equal.
Atmel ATtiny24/44/84 [Preliminary] Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 14-11 on page 111 shows the same timing data, but with the prescaler enabled. Figure 14-11.
Figure 14-12. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Figure 14-13 on page 112 shows the same timing data, but with the prescaler enabled. Figure 14-13.
Atmel ATtiny24/44/84 [Preliminary] 14.11 Register Description 14.11.
Table 14-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 14-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(Note:) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved. 1 0 Clear OC1A/OC1B on Compare Match when up-counting.
Atmel ATtiny24/44/84 [Preliminary] Waveform Generation Mode Bit Description(1) Table 14-4.
When the ICR1 is used as top value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B registers), the ICP1 is disconnected, and, consequently, the input capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to logical zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description.
Atmel ATtiny24/44/84 [Preliminary] A FOC1A/FOC1B strobe will not generate any interrupt, nor will it clear the timer in clear timer on compare match (CTC) mode using OCR1A as top. The FOC1A/FOC1B bits are always read as zero. • Bit 5..0 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to logical zero when the register is written. 14.11.
14.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit 7 6 5 4 3 0x25 (0x45) ICR1[15:8] 0x24 (0x44) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value.
Atmel ATtiny24/44/84 [Preliminary] 14.11.9 TIFR1 – Timer/Counter Interrupt Flag Register 1 Bit 0x0B (0x2B) 7 – 6 – 5 ICIF1 4 – 3 – 2 1 OCF1B OCF1A 0 TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR1 • Bit 7,6,4,3 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to logical zero when the register is written.
15. Timer/Counter Prescaler Timer/counter 0, and 1 share the same prescaler module, but the timer/counters can have different prescaler settings. The description below applies to all timer/counters. Tn is used as a general name, where n = 0, 1. The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
Atmel ATtiny24/44/84 [Preliminary] Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50 duty cycle. Because the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem).
16. USI – Universal Serial Interface 16.1 Features • • • • • • 16.2 Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wakeup from Idle Mode In Two-wire Mode: Wakeup from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability Overview The universal serial interface (USI) provides the basic hardware resources needed for serial communication.
Atmel ATtiny24/44/84 [Preliminary] The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the serial register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected, the counter counts both clock edges.
Figure 16-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 16-3 on page 124. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI shift register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
Atmel ATtiny24/44/84 [Preliminary] 16.3.2 SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master: SPITransfer: out USIDR,r16 ldi r16,(1<
out USICR,r17 in r16,USIDR ret 16.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
Atmel ATtiny24/44/84 [Preliminary] 16.3.4 Two-wire Mode The USI two-wire mode is compliant with the Inter-IC (I2C or TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. Figure 16-4.
Figure 16-5. Two-wire Mode, Typical Timing Diagram SDA SCL S A B 1-7 8 9 1-8 9 1-8 9 ADDRESS R/W ACK DATA ACK DATA ACK C D E P F Referring to the timing diagram (Figure 16-5 on page 128), a bus transfer involves the following steps: 1. The start condition is generated by the Master by forcing the SDA line low while the SCL line is high (A).
Atmel ATtiny24/44/84 [Preliminary] 16.3.5 Start Condition Detector The start condition detector is shown in Figure 16-6 on page 128. The SDA line is delayed (in the range of 50 to 300ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in two-wire mode. The start condition detector is working asynchronously, and can, therefore, wake up the processor from the power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time.
16.5 16.5.1 Register Descriptions USIBR – USI Data Buffer Bit 16.5.2 7 6 5 4 3 2 1 0 0x10 (0x30) MSB LSB Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 USIBR USIDR – USI Data Register Bit 0 0x0F (0x2F) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 USIDR The USI uses no buffering for the serial register, i.e.
Atmel ATtiny24/44/84 [Preliminary] An interrupt will be generated when the flag is set while the USISIE bit in USICR and the global interrupt enable flag are set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the start detection hold of USCL in two-wire mode. A start condition interrupt will wakeup the processor from all sleep modes. • Bit 6 – USIOIF: Counter Overflow Interrupt Flag This flag is set (one) when the 4-bit counter overflows (i.e.
• Bit 7 – USISIE: Start Condition Interrupt Enable Setting this bit to one enables the start condition detector interrupt. If there is a pending interrupt when the USISIE and the global interrupt enable flag are set to one, this will immediately be executed. See the USISIF bit description in “USISR – USI Status Register” on page 130 for further details. • Bit 6 – USIOIE: Counter Overflow Interrupt Enable Setting this bit to one enables the Counter Overflow interrupt.
Atmel ATtiny24/44/84 [Preliminary] • Bit 3..2 – USICS1..0: Clock Source Select These bits set the clock source for the shift register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when using the external clock source (USCK/SCL). When the software strobe or timer/counter 0 compare match clock option is selected, the output latch is transparent and, therefore, the output is changed immediately. Clearing the USICS1..
17. Analog Comparator The analog comparator compares the input values on the positive pin (AIN0) and negative pin (AIN1). When the voltage on the positive pin (AIN0) is higher than the voltage on the negative pin (AIN1), the analog comparator output (ACO) is set. The comparator can trigger a separate interrupt, exclusive to the analog comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle.
Atmel ATtiny24/44/84 [Preliminary] Table 17-1. 17.2 17.2.1 Analog Comparator Multiplexed Input ACME ADEN MUX4..
• Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logical one to the flag.
Atmel ATtiny24/44/84 [Preliminary] 18. Analog-to-Digital Converter 18.1 Features • • • • • • • • • • • • • • • • • 18.2 10-bit Resolution 1.0 LSB Integral Non-linearity ±2 LSB Absolute Accuracy 65 - 260µs Conversion Time Up to 76kSPS at Maximum Resolution Eight Multiplexed Single-Ended Input Channels Twelve differential input channels with selectable gain (1x, 20x) Temperature sensor input channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 1.
Figure 18-1. Analog-to-Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS2...ADTS0 AREF VCC INTERNAL REFERENCE 1.1V TRIGGER SELECT ADC[9:0] ADPS1 ADPS0 ADPS2 ADIF ADSC ADATE ADEN ADLAR MUX4...MUX0 0 ADC DATA REGISTER (ADCH/ADCL) MUX DECODER CHANNEL SELECTION REFS1..REFS0 BIN IPR 15 ADC CTRL. & STATUS A REGISTER (ADCSRA) ADC MULTIPLEXER SELECT (ADMUX) PRESCALER START GAIN SELECTION ADC CTRL.
Atmel ATtiny24/44/84 [Preliminary] If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input pair by the selected gain factor, 1x or 20x, according to the setting of the MUX0 bit in the ADMUX register. This amplified value then becomes the analog input to the ADC. If single-ended channels are used, the gain amplifier is bypassed altogether.
Figure 18-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC interrupt flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in free running mode, constantly sampling and updating the ADC data register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
Atmel ATtiny24/44/84 [Preliminary] The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single-ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles.
Figure 18-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Prescaler Reset Conversion Complete MUX and REFS Update Figure 18-7.
Atmel ATtiny24/44/84 [Preliminary] 18.6 Changing Channel or Reference Selection The MUX5:0 and REFS1:0 bits in the ADMUX register are single-buffered through a temporary register to which the CPU has random access. This ensures that the channel and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started.
18.7 ADC Noise Canceller The ADC features a noise canceller that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceller can be used with ADC noise reduction and idle modes. To make use of this feature, the following procedure should be used: a. Make sure that the ADC is enabled and is not busy converting. Single-conversion mode must be selected and the ADC conversion complete interrupt must be enabled. b.
Atmel ATtiny24/44/84 [Preliminary] Figure 18-8. Analog Input Circuitry IIH ADCn 1..100 kΩ CS/H= 14 pF IIL VCC/2 18.7.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible.
• Gain Error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5LSB below maximum). Ideal value: 0LSB Figure 18-10. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain errors, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0LSB. Figure 18-11.
Atmel ATtiny24/44/84 [Preliminary] Figure 18-12. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1LSB wide) will code to the same value. Always ±0.5LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
The voltage of the positive pin must always be larger than the voltage of the negative pin or otherwise the voltage difference is saturated to zero. The result is presented in one-sided form, from 0x000 (0d) through 0x3FF (+1023d). The GAIN is either 1x or 20x. 18.8.
Atmel ATtiny24/44/84 [Preliminary] To obtain best accuracy the coefficient k should be measured using two temperature calibrations. Using offset calibration, set k = 1.0, where k = (1024*1.07mV/°C)/1.1V~1.0 [1/°C]. 18.10 Register Description 18.10.
Table 18-4. Single Ended Input Channel Selections. Single Ended Input MUX5..0 ADC0 (PA0) 000000 ADC1 (PA1) 000001 ADC2 (PA2) 000010 ADC3 (PA3) 000011 ADC4 (PA4) 000100 ADC5 (PA5) 000101 ADC6 (PA6) 000110 ADC7 (PA7) 000111 Reserved for differential channels(1) 001000 - 011111 0V (AGND) 100000 1.1V (I Ref) 100001 (2) ADC8 Notes: 100010 Reserved for offset calibration(3) 100011 - 100111 Reserved for reversal differential channels(1) 101000 - 111111 1.
Atmel ATtiny24/44/84 [Preliminary] Table 18-5. Differential Input channel Selections. Positive Differential Input ADC0 (PA0) ADC1 (PA1) MUX5..
18.10.2 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 0x06 (0x26) ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to logical one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress will terminate the conversion.
Atmel ATtiny24/44/84 [Preliminary] Table 18-6. 18.10.3 18.10.3.1 ADPS2 ADPS1 ADPS0 Division Factor 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 ADCL and ADCH – ADC Data Register ADLAR = 0 Bit 15 14 13 12 11 10 9 8 0x05 (0x25) – – – – – – ADC9 ADC8 ADCH 0x04 (0x24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial Value 18.10.3.
18.10.4 ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 0x03 (0x23) BIN ACME – ADLAR – ADTS2 ADTS1 ADTS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bits 7 – BIN: Bipolar Input Mode The gain stage is working in the unipolar mode by default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register.
Atmel ATtiny24/44/84 [Preliminary] Table 18-7. 18.10.
19. debugWIRE On-chip Debug System 19.1 Features • • • • • • • • • • 19.
Atmel ATtiny24/44/84 [Preliminary] When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20kΩ. However, the pull-up resistor is optional. • Connecting the RESET pin directly to VCC will not work. • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 19.
20. Self-Programming the Flash The device provides a self-programming mechanism (SPM) for downloading and uploading program code by the MCU itself. The self programming can use any available data interface and associated protocol to read code and write (program) that code into program memory. Program memory is updated in a page-by-page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
Atmel ATtiny24/44/84 [Preliminary] 20.3 Performing a Page Write To execute a page write, set up the address in the Z-pointer, write "00000101" to SPMCSR, and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 are ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. The CPU is halted during the page write operation. 20.
20.4.1 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to flash. Reading the fuses and lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user check the status bit (EEPE) in the EECR register and verify that the bit is cleared before writing to SPMCSR. 20.4.2 Reading the Lock and Fuse Bits from Software It is possible to read both the lock and fuse bits from software.
Atmel ATtiny24/44/84 [Preliminary] Flash corru ptio n ca n e asily b e avoided by fo llowing at lea st one the se d esig n recommendations: 1. Keep the Atmel® AVR® RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC reset protection circuit can be used.
The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. • Bit 1 – PGERS: Page Erase If this bit is written to logical one at the same time as SPMEN, the next SPM instruction within four clock cycles executes a page erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored.
Atmel ATtiny24/44/84 [Preliminary] 21. Memory Programming This section describes the different methods for programming the Atmel ® ATtiny24/44/84 memories. 21.1 Program And Data Memory Lock Bits The ATtiny24/44/84 provides two lock bits which can be left unprogrammed (set to one) or can be programmed (set to zero) to obtain the additional security listed in Table 21-2 on page 163. The lock bits can only be erased to one with the chip erase command.
21.2 Fuse Bytes The Atmel® ATtiny24/44/84 has three fuse bytes. Table 21-4 on page 164 to Table 21-5 on page 165 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero ("0") if they are programmed. Table 21-3. Fuse Extended Byte Fuse High Byte SELFPRGEN Table 21-4.
Atmel ATtiny24/44/84 [Preliminary] Table 21-5.
21.5 Page Size Table 21-7. Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB ATtiny24 1K words (2K bytes) 16 words PC[3:0] 64 PC[9:4] 9 ATtiny44 2K words (4K bytes) 32 words PC[4:0] 64 PC[10:5] 10 ATtiny84 4K words (8K bytes) 32 words PC[4:0] 128 PC[11:5] 11 Table 21-8. Device 166 No. of Words in a Page and No. of Pages in the Flash No. of Words in a Page and No. of Pages in the EEPROM EEPROM Size Page Size PCWORD No.
Atmel ATtiny24/44/84 [Preliminary] 21.6 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 21-9 on page 167, the pin mapping for SPI programming is listed.
21.6.1 Serial Programming Algorithm When writing serial data to the Atmel® AVR® ATtiny24/44/84, data are clocked on the rising edge of SCK. When reading data from the Atmel ATtiny24/44/84, data are clocked on the falling edge of SCK. See Figure 22-3 and Figure 22-4 for timing details. To program and verify the Atmel ATtiny24/44/84 in the serial programming mode, the following sequence is recommended (see four-byte instruction formats in Table 21-11): 1.
Atmel ATtiny24/44/84 [Preliminary] 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Table 21-10. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location 21.6.2 Symbol Minimum Wait Delay tWD_FLASH 4.5ms tWD_EEPROM 4.0ms tWD_ERASE 4.0ms tWD_FUSE 4.5ms Serial Programming Instruction set Table 21-11 on page 169 and Figure 21-2 on page 170 describes the Instruction set. Table 21-11.
Table 21-11. Serial Programming Instruction Set (Continued) Instruction Format (1) Byte 1 Byte 2 Byte 3 Byte4 Write Fuse bits $AC $A0 $00 data byte in Write Fuse High bits $AC $A8 $00 data byte in Write Extended Fuse Bits $AC $A4 $00 data byte in Instruction/Operation Notes: 1. 2. 3. 4. 5. 6. 7. Not all instructions are applicable for all parts. adr = address Bits are programmed ‘0’, unprogrammed ‘1’.
Atmel ATtiny24/44/84 [Preliminary] 21.7 High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the Atmel® ATtiny24/44/84. Figure 21-3. High-voltage Serial Programming +11.5 - 12.5V SCI +1.8 - 5.5V PB3 (RESET) VCC PB0 PA4 SDO PA5 SII PA6 SDI GND Table 21-12.
21.8 High-voltage Serial Programming Algorithm To program and verify the Atmel® AVR® ATtiny24/44/84 in the high-voltage serial programming mode, the following sequence is recommended (see instruction formats in Table 21-15 on page 175): 21.8.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET pin to “0” and toggle SCI at least six times. 3.
Atmel ATtiny24/44/84 [Preliminary] 21.8.3 Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories, as well as lock bits. The lock bits are not reset until the program memory has been completely erased. The fuse bits are not changed. A chip erase must be performed before the flash and/or EEPROM are reprogrammed. Note: 1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. 1. Load "Chip Erase" command (see Table 21-15 on page 175). 2. Wait after Instr.
Figure 21-5. High-voltage Serial Programming Waveforms SDI PB0 MSB LSB SII PB1 MSB LSB SDO PB2 SCI PB3 21.8.5 MSB 0 LSB 1 2 3 4 5 6 7 8 9 10 Programming the EEPROM The EEPROM is organized in pages, see Table 22-8 on page 185. When programming the EEPROM, the data are latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to Table 21-15 on page 175): 1.
Atmel ATtiny24/44/84 [Preliminary] Table 21-15. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 Instruction Format Instruction Chip Erase Load “Write Flash” Command Load Flash Page Buffer Instr.1/5 Instr.2/6 Instr.3/7 SDI 0_1000_0000_00 0_0000_0000_00 0_0000_0000_00 SII 0_0100_1100_00 0_0110_0100_00 0_0110_1100_00 SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx SDI 0_0001_0000_00 SII 0_0100_1100_00 SDO x_xxxx_xxxx_xx Instr.4 Wait after Instr.
Table 21-15. High-voltage Serial Programming Instruction Set for ATtiny24/44/84 (Continued) Instruction Format Instruction Instr.1/5 Instr.2/6 Instr.3/7 Instr.
Atmel ATtiny24/44/84 [Preliminary] Note: a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bits, q = data out low bits, x = don’t care, 1 = Lock Bit1, 2 = Lock Bit2, 3 = CKSEL0 Fuse, 4 = CKSEL1 Fuse, 5 = CKSEL2 Fuse, 6 = CKSEL3 Fuse, 7 = SUT0 Fuse, 8 = SUT1 Fuse, 9 = CKDIV8 Fuse, A = CKOUT Fuse, B = BODLEVEL0 Fuse, C = BODLEVEL1 Fuse, D= BODLEVEL2 Fuse, E = EESAVE Fuse, F = WDTON Fuse, G = SPIEN Fuse, H = DWEN Fuse, I = RSTDISBL Fuse Notes: 1.
22. Electrical Characteristics 22.1 Absolute Maximum Ratings Automotive Operating Temperature ...............–40°C to +125°C *NOTICE: Storage Temperature .....................................–65°C to +150°C Voltage on any Pin except RESET with respect to Ground ...............................–0.5V to VCC+0.5V Voltage on RESET with respect to GND......... –0.5V to +13.0V Voltage on VCC with respect to GND .................. –0.5V to 6.
Atmel ATtiny24/44/84 [Preliminary] DC Characteristics TA = -40°C to 125°C, VCC = 2.7V to 5.5V (unless otherwise noted)(1) (Continued) Table 22-1. Symbol Parameter Condition Power Supply Current ICC Power-down mode IACLK Analog Comparator Input Leakage Current Min. Typ. Max. Units Active 1MHz, VCC = 3V 0.4 1.5 mA Active 4MHz, VCC = 3V 1.8 3.0 mA Active 8MHz, VCC = 5V 5.0 10.0 mA Idle 1MHz, VCC = 3V 0.075 0.2 mA Idle 4MHz, VCC = 3V 0.3 0.5 mA Idle 8MHz, VCC = 5V 1.2 2.
22.3 Clock Characterizations 22.3.1 Calibrated Internal RC Oscillator Accuracy Table 22-2. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Accuracy 8.0MHz 3V 25°C ±2% User Calibration 7.3 - 8.1MHz 2.7V - 5.5V -40°C - 125°C ±20% Oscillator Jitter 8.0MHz 2.7V - 5.5V -40°C - 125° Factory Calibration Note: Standard Deviation 0.4ns(1) 1.
Atmel ATtiny24/44/84 [Preliminary] 22.4 System and Reset Characterizations Table 22-4. Symbol VHYST VRAM2. Reset, Brown-out and Internal Voltage Reference Characteristics(1) Parameter Condition Brown-out Detector Hysteresis RAM Retention Voltage (1) Typ Max Units 100 250 mV 50 tBOD Min Pulse Width on Brown-out Reset VBG Bandgap reference voltage VC C= 2.7V, TA = 25°C tBG Bandgap reference start-up time IBG Bandgap reference current consumption Notes: Min mV 2 1.0 ns 1.1 1.
22.5 ADC Characteristics – Preliminary Data Table 22-6. ADC Characteristics, Single Ended Channels. -40°C - 125°C Symbol Parameter Resolution Condition Min Typ Max Units Single-ended conversion 10 Single-ended conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 2.0 4.0 LSB Single-ended conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz Noise Reduction Mode 2.0 4.0 LSB INL Integral Non-linearity (INL) Single-ended conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 0.5 1.
Atmel ATtiny24/44/84 [Preliminary] Table 22-7. Symbol ADC Characteristics, Differential Channels, TA = -40°C to 125°C Parameter Condition Min Typ Max Units Gain = 1x 8 Bits Gain = 20x 8 Bits Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz 2.5 5.0 LSB Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz 3.0 6.0 LSB Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz 0.5 2.5 LSB Bipolar - Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz 0.5 3.
Table 22-7. Symbol ADC Characteristics, Differential Channels, TA = -40°C to 125°C (Continued) Parameter Offset Error VREF VIN VDIFF 22.6 Condition Min Typ Max Units Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz -5.0 2.0 5.0 LSB Bipolar - Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz -5.0 2.0 5.0 LSB Unipolar - Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200kHz -6.5 2.0 6.5 LSB Clock Frequency 50 200 kHz Conversion Time 65 260 µs Reference Voltage 2.
Atmel ATtiny24/44/84 [Preliminary] Table 22-8. Serial Programming Characteristics, TA = -40°C to 125°C, VCC = 2.7 - 5.5V (Unless Otherwise Noted) Symbol Parameter 1/tCLCL Oscillator Frequency (Atmel ATtiny24/44/84V) Oscillator Period (Atmel ATtiny24/44/84V) tCLCL Min Typ 0 Max Units 4 MHz 250 ns Oscillator Frequency (ATtiny24/44/84, VCC = 4.5V 5.5V) 0 tCLCL Oscillator Period (ATtiny24/44/84, VCC = 4.5V 5.
22.7 High-voltage Serial Programming Characteristics Figure 22-5. High-voltage Serial Programming Timing CC CK Table 22-9. Symbol Parameter Min tSHSL SCI (PB0) Pulse Width High 110 ns tSLSH SCI (PB0) Pulse Width Low 110 ns tIVSH SDI (PA6), SII (PB1) Valid to SCI (PB0) High 50 ns tSHIX SDI (PA6), SII (PB1) Hold after SCI (PB0) High 50 ns tSHOV SCI (PB0) High to SDO (PA4) Valid 16 ns Wait after Instr. 3 for Write Fuse Bits 2.
Atmel ATtiny24/44/84 [Preliminary] 23. Typical Characteristics – Preliminary Data The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing.
Figure 23-2. Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) - Temp.=125°C ACTIVE S UP P LY CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz - Temperature = 125˚C 1.2 5.5 V 1 5.0 V ICC (mA) 0.8 4.5 V 0.6 3.3 V 3.0 V 2.7 V 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 23-3. Active Supply Current vs. frequency (1 - 20MHz) - Temp.=25°C ACTIVE S UP P LY CURRENT vs . FREQUENCY 1 - 20 MHz - Temperature = 25˚C 25 ICC (mA) 20 15 5.5 V 5.0 V 4.5 V 10 3.3 V 3.
Atmel ATtiny24/44/84 [Preliminary] Figure 23-4. Active Supply Current vs. frequency (1 - 20MHz) - Temp.=125°C ACTIVE S UP P LY CURRENT vs . FREQUENCY 1 - 20 MHz - Temperature = 125˚C 25 ICC (mA) 20 15 5.5 V 5.0 V 4.5 V 10 3.3 V 3.0 V 2.7 V 5 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 23-5. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) ACTIVE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 8 MHz 7 125 85 25 -45 6 ICC (mA) 5 ˚C ˚C ˚C ˚C 4 3 2 1 0 2.
Figure 23-6. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) ACTIVE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 1MHz 1.4 125 85 25 -40 1.2 ICC (mA) 1 ˚C ˚C ˚C ˚C 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-7. Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) ACTIVE S UP P LY CURRENT vs . V CC INTERNAL RC OSCILLATOR, 128 KHz 0.2 ICC (mA) 0.16 -40 ˚C 25 ˚C 85 ˚C 125 ˚C 0.12 0.08 0.04 0 2.5 3 3.5 4 4.5 5 5.
Atmel ATtiny24/44/84 [Preliminary] 23.2 Idle Supply Current Figure 23-8. Idle Supply Current vs. Low Frequency (0.1 - 1.0MHz) IDLE S UP P LY CURRENT vs . LOW FREQUENCY 0.1 - 1.0 MHz - Temperature= 125˚C 0.012 5.5 V 0.01 ICC (mA) 5.0 V 0.008 4.5 V 0.006 3.3 V 3.0 V 2.7 V 0.004 0.002 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 23-9. Idle Supply Current vs. Frequency (1 - 20MHz) IDLE S UP P LY CURRENT vs . FREQUENCY 1 - 20 MHz - Temperature = 125 ˚C 4 ICC (mA) 3.
Figure 23-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) IDLE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 8 MHz 2 1.8 1.6 ICC (mA) 1.4 125 85 25 -40 ˚C ˚C ˚C ˚C 125 85 25 -40 ˚C ˚C ˚C ˚C 1.2 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-11. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) IDLE S UP P LY CURRENT vs . VC C INTERNAL RC OSCILLATOR, 1 MHz 0.35 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 2.5 3 3.5 4 4.5 5 5.
Atmel ATtiny24/44/84 [Preliminary] Figure 23-12. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) IDLE S UP P LY CURRENT vs . VCC INTERNAL RC OSCILLATOR, 128 KHz 0.035 125 85 25 -40 0.03 ICC (mA) 0.025 ˚C ˚C ˚C ˚C 0.02 0.015 0.01 0.005 0 2.5 3 3.5 4 4.5 5 5.
23.3 Supply Current of IO modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See “Power Reduction Register” on page 36 for details. Table 23-1. Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers VCC = 2V, F = 1MHz 23.
Atmel ATtiny24/44/84 [Preliminary] Figure 23-14. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) P OWER-DOWN S UP P LY CURRENT vs . VC C WATCHDOG TIMER ENABLED 10 9 8 ICC (uA) 7 6 5 4 125 -45 85 25 3 2 1 ˚C ˚C ˚C ˚C 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 23.5 Pin Pull-up Figure 23-15. I/O Pin Pull-up Resistor Current vs. input Voltage (VCC = 2.7V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE V CC = 2.7V 90 80 70 IOP (uA) 60 50 40 30 20 -45 25 85 125 10 0 0 0.5 1 1.
Figure 23-16. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O P IN P ULL-UP RES IS TOR CURRENT vs . INP UT VOLTAGE V CC = 5.0V 160 140 120 IOP (uA) 100 80 60 40 -45 25 85 125 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 ˚C ˚C ˚C ˚C 5 V OP (V) Figure 23-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vc c = 2.7V 60 -40 ˚C 50 125 ˚C IRE S E T (uA) 40 30 20 10 0 0 0.5 1 1.5 2 2.
Atmel ATtiny24/44/84 [Preliminary] Figure 23-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RES ET P ULL-UP RES IS TOR CURRENT vs . RES ET P IN VOLTAGE Vc c = 5.0V 120 -40 ˚C 100 125 ˚C IRE S E T (uA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 V RE S E T (V) 23.6 Pin Driver Strength Figure 23-19. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT LOW POWER PINS @ Vcc = 3V 0.06 125 ˚C 0.05 V OL (V) 0.
Figure 23-20. I/O pin Output Voltage vs. Sink Current (VCC = 5V) I/O P IN OUTP UT VOLTAGE vs . S INK CURRENT LOW POWER PINS - Vcc = 5.0V 0.7 125 ˚C 0.6 85 ˚C 0.5 V OL (V) 25 ˚C 0.4 -45 ˚C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 23-21. I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT LOW POWER PINS @ vcc = 3V 3.5 V OH (V) 3 2.5 -45 ˚C 25 ˚C 85 ˚C 125 ˚C 2 1.
Atmel ATtiny24/44/84 [Preliminary] Figure 23-22. I/O Pin output Voltage vs. Source Current (VCC = 5V) I/O P IN OUTP UT VOLTAGE vs . S OURCE CURRENT LOW POWER PINS @ vcc = 5V 5.1 5 4.9 V OH (V) 4.8 4.7 4.6 -45 ˚C 4.5 25 ˚C 4.4 85 ˚C 125 ˚C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) 23.7 Pin Threshold and Hysteresis Figure 23-23. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’) I/O P IN INP UT THRES HOLD VOLTAGE vs . V CC VIH, IO PIN READ AS '1' 3.
Figure 23-24. I/O Pin Input threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’) I/O P IN INP UT THRES HOLD VOLTAGE vs . V C C VIL, IO PIN READ AS '0' 2.5 125 85 25 -40 ˚C ˚C ˚C ˚C 125 85 -20 -40 ˚C ˚C ˚C ˚C Thre s hold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-25. I/O Pin Input Hysteresis vs. VCC I/O P IN INP UT HYS TERES IS vs . V CC 0.5 0.45 Input Hys te re s is (mV) 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 2.5 3 3.5 4 4.5 5 5.
Atmel ATtiny24/44/84 [Preliminary] Figure 23-26. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Threshold as ‘1’) RES ET P IN AS I/O THRES HOLD VOLTAGE vs . VCC VIH, RESET READ AS '1' 3 Thre s hold (V) 2.5 125 85 25 -40 ˚C ˚C ˚C ˚C 125 85 25 -45 ˚C ˚C ˚C ˚C 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-27. Reset Input Threshold Voltage vs. VCC (VIL, IO pin Read as ‘0’) RES ET P IN AS I/O THRES HOLD VOLTAGE vs . V C C VIL, RESET READ AS '0' 3 Thre s hold (V) 2.5 2 1.
Figure 23-28. Reset Pin Input Hysteresis vs. VCC RES ET P IN INP UT HYS TERES IS vs . V C C 1 0.9 Input Hys te re s is (mV) 0.8 0.7 0.6 -40 ˚C 0.5 0.4 25 ˚C 0.3 0.2 85 ˚C 0.1 125 ˚C 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 23.8 BOD Threshold and Analog Comparator Offset Figure 23-29. BOD Threshold vs. Temperature (BODLEVEL is 4.3V) BANDGAP VOLTAGE vs . TEMP ERATURE BOD = 4.3V 4.4 1 Thre s hold (V) 4.35 4.3 0 4.25 4.2 4.
Atmel ATtiny24/44/84 [Preliminary] Figure 23-30. BOD Threshold vs, Temperature (BODLEVEL is 2.7V) BANDGAP VOLTAGE vs . TEMP ERATURE BOD = 2.7V 2.78 1 2.76 Thre s hold (V) 2.74 2.72 2.7 0 2.68 2.66 2.64 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (C) Figure 23-31. BOD Threshold vs. Temperature (BODLEVEL is 1.8V) BANDGAP VOLTAGE vs . TEMP ERATURE BOD = 1.8V 1.85 1.84 1 Thre s hold (V) 1.83 1.82 1.81 0 1.8 1.79 1.
23.9 Internal Oscillator Speed Figure 23-32. Watchdog Oscillator Frequency vs. VCC WATCHDOG OS CILLATOR FREQUENCY vs . OP ERATING VOLTAGE 124 122 -40 ˚C 120 FRC (kHz ) 118 25 ˚C 116 114 112 85 ˚C 110 108 125 ˚C 106 104 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-33. Calibrated 8MHz RC Oscillator Frequency vs. VCC CALIBRATED 8.0MHz RC OS CILLATOR FREQUENCY vs . OP ERATING VOLTAGE 9 8.5 -40 25 85 125 FRC (MHz ) 8 ˚C ˚C ˚C ˚C 7.5 7 6.5 6 2.5 3 3.5 4 4.5 5 5.
Atmel ATtiny24/44/84 [Preliminary] Figure 23-34. Calibrated 8MHz RC oscillator Frequency vs. Temperature CALIBRATED 8.0MHz RC OS CILLATOR FREQUENCY vs . TEMP ERATURE 8.4 8.3 5.0 V 3.0 V FRC (MHz ) 8.2 8.1 8 7.9 7.8 7.7 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature Figure 23-35. Calibrated 8MHz RC Oscillator Frequency vs, OSCCAL Value CALIBRATED 8.0MHz RC OS CILLATOR FREQUENCY vs .
23.10 Current Consumption of Peripheral Units Figure 23-36. ADC Current vs. VCC ADC CURRENT vs . VC C 4.0 MHZ FREQUENCY 125 85 25 -40 700 600 ˚C ˚C ˚C ˚C ICC (uA) 500 400 300 200 100 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-37. AREF External Reference Current vs. VCC AREF CURRENT vs . AREF VOLTAGE WHEN US ED AS ADC REFERENCE (Vc c =5.5V) 14 25 ˚C AREF pin c urre nt (uA) 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Atmel ATtiny24/44/84 [Preliminary] Figure 23-38. Analog Comparator Current vs. VCC ADC CURRENT vs . VC C 4.0 MHZ FREQUENCY 100 -40 25 85 125 90 80 ˚C ˚C ˚C ˚C ICC (uA) 70 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 23-39. Programming Current vs. VCC I/O MODULE CURRENT vs . VCC 4.0 MHZ FREQUENCY 12000 25 ˚C 10000 ICC (uA) 8000 6000 4000 2000 0 2.5 3.5 4.5 5.
Figure 23-40. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs V C C 30 -40 25 85 125 25 ˚C ˚C ˚C ˚C ICC (uA) 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 23.11 Current Consumption in Reset and Reset Pulse width Figure 23-41. Reset Supply Current vs. VCC (0.1 - 1.0MHz, excluding Current Through the Reset Pull-up) RES ET S UP P LY CURRENT vs . VC C EXCLUDING CURRENT THROUGH THE RESET PULLUP 0.2 5.5 V 0.18 5.0 V 0.16 4.5 V ICC (mA) 0.14 0.12 3.3 V 3.0 V 2.7 V 0.1 0.08 0.06 0.
Atmel ATtiny24/44/84 [Preliminary] Figure 23-42. Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through the Reset Pull-up) RES ET S UP P LY CURRENT vs . V C C EXCLUDING CURRENT THROUGH THE RESET PULLUP 3 2.5 5.5 V 5.0 V 2 ICC (mA) 4.5 V 1.5 3.6 3.3 3.0 2.7 1 V V V V 0.5 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 23-43. Minimum Reset Pulse Width vs. VCC MINIMUM RES ET P ULS E WIDTH vs .
24.
Atmel ATtiny24/44/84 [Preliminary] Note: 1. For compatibility with future devices, reserved bits should be written to logical zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them.
25.
Atmel ATtiny24/44/84 [Preliminary] Mnemonics Operands Description Operation Flags #Clocks ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)←Rd(n),C←Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)←Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ←Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
26. Ordering Information 26.1 ATtiny24/44/84 Ordering Code Speed (MHz)(3) Power Supply (V) Package(1)(2) Operation Range ATtiny24-15SSZ 16 2.7 - 5.5 TU Automotive (-40° to +125°C) ATtiny24-15MZ 16 2.7 - 5.5 PC Automotive (-40° to +125°C) ATtiny44-15SSZ 16 2.7 - 5.5 TU Automotive (-40° to +125°C) ATtiny44-15MZ 16 2.7 - 5.5 PC Automotive (-40° to +125°C) ATtiny84-15MZ 16 2.7 - 5.5 PC Automotive (-40° to +125°C) Notes: 1. Green and ROHS packaging 2.
Atmel ATtiny24/44/84 [Preliminary] 27. Packaging Information 27.
27.
Atmel ATtiny24/44/84 [Preliminary] 28. Errata The revision letter in this section refers to the revision of the Atmel® ATtiny24/44/84 Automotive device. 28.1 28.1.1 ATtiny24 Automotive Rev. E 1. No known errata. 28.2 28.2.1 ATtiny44 Automotive Rev. D 1. No known errata. 28.3 28.3.1 ATtiny84 Automotive Rev. B 1. No known errata.
29. Datasheet Revision History 29.1 Rev F 10/12 1. Section 27 “Packaging Information” on page 214 updated. 29.2 Rev E 02/11 1. MCUCR registers updated. 29.3 Rev D 09/10 1. BOD values updated. 29.4 Rev C 11/08 1. Internal RC oscillator accuracy update. See “Calibrated Internal RC Oscillator” on page 29. 2. ADC characteristics update. See “ADC Characteristics – Preliminary Data” on page 182. 3. DC characteristics update. See Table 22-1 on page 178. 4.
Atmel ATtiny24/44/84 [Preliminary] 30. Table of Contents Features .................................................................................................. 1 1 Pin Configurations ................................................................................ 2 1.1 2 Disclaimer ......................................................................................................2 Overview ................................................................................................ 3 2.
8 9 7.8 128kHz Internal Oscillator ............................................................................31 7.9 System Clock Prescaler ...............................................................................31 7.10 Register Description .....................................................................................32 Power Management and Sleep Modes .............................................. 34 8.1 Sleep Modes ...................................................................
Atmel ATtiny24/44/84 [Preliminary] 13 8-bit Timer/Counter0 with PWM ......................................................... 72 13.1 Features .......................................................................................................72 13.2 Overview ......................................................................................................72 13.3 Timer/Counter Clock Sources ......................................................................73 13.4 Counter Unit .............
18 Analog-to-Digital Converter ............................................................. 137 18.1 Features .....................................................................................................137 18.2 Overview ....................................................................................................137 18.3 ADC Operation ...........................................................................................138 18.4 Starting a Conversion ..............................
Atmel ATtiny24/44/84 [Preliminary] 22 Electrical Characteristics ................................................................. 178 22.1 Absolute Maximum Ratings ........................................................................178 22.2 Speed Grades ............................................................................................179 22.3 Clock Characterizations .............................................................................180 22.
29 Datasheet Revision History .............................................................. 218 29.1 Rev E 02/11 ...............................................................................................218 29.2 Rev D 09/10 ...............................................................................................218 29.3 Rev C 11/08 ...............................................................................................218 29.4 Rev B 09/07 ...........................................
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