Datasheet

97
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Figure 35. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
clk_I/O
/8)
Figure 36 on page 97 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where
OCR0A is TOP.
Figure 36. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f
clk_I/O
/8)
11.9 Register Description
11.9.1 TCCR0A – Timer/Counter Control Register A
z Bits 7:6 – COM0A[1:0] : Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A[1:0] bits are set, the OC0A
output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction
Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
Bit 7 6 5 4 3 2 1 0
0x24 (0x44)
COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0