Datasheet

96
ATtiny828 [DATASHEET]
8371A–AVR–08/12
At the very start of period 2 in Figure 32 on page 95 OCnx has a transition from high to low even though there is no
Compare Match. The point of this transition is to guaratee symmetry around BOTTOM. There are two cases that give a
transition without Compare Match.
z OCR0x changes its value from TOP, like in Figure 32 on page 95. When the OCR0x value is TOP the OCnx pin
value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the
OCnx value at TOP must correspond to the result of an up-counting Compare Match.
z The timer starts counting from a value higher than the one in OCR0x, and for that reason misses the Compare
Match and hence the OCnx change that would have happened on the way up.
11.8 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore shown as a clock enable signal in the
following figures. The figures include information on when Interrupt Flags are set. Figure 33 on page 96 contains timing
data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other
than phase correct PWM mode.
Figure 33. Timer/Counter Timing Diagram, no Prescaling
Figure 34 on page 96 shows the same timing data, but with the prescaler enabled.
Figure 34. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 35 on page 97 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM
mode, where OCR0A is TOP.
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)