Datasheet

85
ATtiny828 [DATASHEET]
8371A–AVR–08/12
10.4.13 PINB – Port B Input Pins
z Bits 7:0 – PINB[7:0]: Port Input Data
Regardless of the setting of the data direction bit, the value of the port pin PBn can be read through the PINBn bit.
Writing a logic one to PINBn toggles the value of PORTBn, regardless of the value in DDBn.
10.4.14 PUEA – Port A Pull-Up Enable Control Register
z Bits 7:0 – PUEA[7:0]: Pull-Up Enable Bits
When a pull-up enable bit, PUEAn, is set the pull-up resistor on the equivalent port pin, PAn, is enabled.
10.4.15 PORTA – Port A Data Register
z Bits 7:0 – PORTA[3:0]: Port Data Bits
When pin PAn is configured as an output, setting PORTAn will drive PAn high. Clearing PORTAn will drive PAn low.
When the pin is configured as an input the value of the PORTxn bit doesn’t matter. See Table 19 on page 61.
10.4.16 DDRA – Port A Data Direction Register
z Bits 7:0 – DDA[7:0]: Data Direction Bits
When DDAn is set, the pin PAn is configured as an output. When DDAn is cleared, the pin is configured as an input.
Bit 76543210
0x04 (0x24)
PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
0x03 (0x23)
PUEA7 PUEA6 PUEA5 PUEA4 PUEA3 PUEA2 PUEA1 PUEA0 PUEA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x02 (0x22)
PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x01 (0x21)
DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000