Datasheet

83
ATtiny828 [DATASHEET]
8371A–AVR–08/12
10.4.5 PIND – Port D Input Pins
z Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
z Bits 3:0 – PIND[3:0]: Port Input Data
Regardless of the setting of the data direction bit, the value of the port pin PDn can be read through the PINDn bit.
Writing a logic one to PINDn toggles the value of PORTDn, regardless of the value in DDDn.
10.4.6 PUEC – Port C Pull-Up Enable Control Register
z Bits 7:0 – PUEC[7:0]: Pull-Up Enable Bits
When a pull-up enable bit, PUECn, is set the pull-up resistor on the equivalent port pin, PCn, is enabled.
10.4.7 PORTC – Port C Data Register
z Bits 7:0 – PORTC[3:0]: Port Data Bits
When pin PCn is configured as an output, setting PORTCn will drive PCn high. Clearing PORTCn will drive PCn low.
When the pin is configured as an input the value of the PORTxn bit doesn’t matter. See Table 19 on page 61.
10.4.8 DDRC – Port C Data Direction Register
z Bits 7:0 – DDC[7:0]: Data Direction Bits
When DDCn is set, the pin PCn is configured as an output. When DDCn is cleared, the pin is configured as an input.
Bit 76543210
0x0C (0x2C)
– – – – PIND3 PIND2 PIND1 PIND0 PIND
Read/Write R R R R R/W R/W R/W R/W
Initial Value N/A N/A N/A N/A N/A N/A N/A N/A
Bit 76543210
0x0B (0x2B)
PUEC7 PUEC6 PUEC5 PUEC4 PUEC3 PUEC2 PUEC1 PUEC0 PUEC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x0A (0x2A)
PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x09 (0x29)
DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000