Datasheet

82
ATtiny828 [DATASHEET]
8371A–AVR–08/12
10.4.2 PUED – Port D Pull-Up Enable Control Register
z Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
z Bits 3:0 – PUED[3:0]: Pull-Up Enable Bits
When a pull-up enable bit, PUEDn, is set the pull-up resistor on the equivalent port pin, PDn, is enabled.
10.4.3 PORTD – Port D Data Register
z Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
z Bits 3:0 – PORTD[3:0]: Port Data Bits
When pin PDn is configured as an output, setting PORTDn will drive PDn high. Clearing PORTDn will drive PDn low.
When the pin is configured as an input the value of the PORTxn bit doesn’t matter. See Table 19 on page 61.
10.4.4 DDRD – Port D Data Direction Register
z Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
z Bits 3:0 – DDD[3:0]: Data Direction Bits
When DDDn is set, the pin PDn is configured as an output. When DDDn is cleared, the pin is configured as an input.
Bit 76543210
0x0F (0x2F)
– – – – PUED3 PUED2 PUED1 PUED0 PUED
Read/Write R R R R R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x0E (0x2E)
– – – – PORTD3 PORTD2 PORTD1 PORTD0 PORTD
Read/Write R R R R R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x0D (0x2D)
– – – – DDD3 DDD2 DDD1 DDD0 DDRD
Read/Write R R R R R/W R/W R/W R/W
Initial Value00000000