Datasheet

81
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Note: 1. RSTDISBL is 1 when the fuse bit is “0” (programmed)
10.4 Register Description
10.4.1 PHDE – Port High Drive Enable Register
z Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
z Bit 2 – PHDEC: Port C High Drive Enable
When this bit is set the extra high sink capability of port C is enabled.
z Bits 1:0 – Res: Reserved Bits
These bits are reserved and will always read zero.
PD3
PUOE 0
PUOV 0
DDOE TWEN + (SPE z MSTR)
DDOV TWEN z SCL_OUT
PVOE TWEN + (SPE z MSTR)
PVOV TWEN z SPE z MSTR z SCK_OUT
PTOE 0
DIEOE (PCINT27 • PCIE3) + ADC27D
DIEOV PCINT27 • PCIE3
DI PCINT27 Input / SCK_IN
AIO ADC27 Input / SCL_IN
Pin Signal Composition
Bit 76543210
0x14 (0x34)
– – – – – PHDEC – – PHDE
Read/Write R R R R R R/W R R
Initial Value00000000