Datasheet

80
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Table 28. Override Signals of Port D
Pin Signal Composition
PD0
PUOE 0
PUOV 0
DDOE TWEN + (SPE z MSTR)
DDOV TWEN z SDA_OUT
PVOE TWEN + (SPE z MSTR)
PVOV TWEN z SPE z MSTR z SPI_MSTR_OUT
PTOE 0
DIEOE (PCINT24 • PCIE3) + ADC24D
DIEOV PCINT24 • PCIE3
DI PCINT24 Input / SPI_SLAVE_IN
AIO ADC24 Input / SDA_IN
PD1
PUOE 0
PUOV 0
DDOE SPE z MSTR
DDOV 0
PVOE SPE z MSTR
PVOV SPI_SLAVE_OUT
PTOE 0
DIEOE (PCINT25 • PCIE3) + ADC25D
DIEOV PCINT25 • PCIE3
DI PCINT25 Input / SPI_MASTER_IN
AIO ADC25 Input
PD2
PUOE RSTDISBL
(1)
PUOV 1
DDOE RSTDISBL
(1)
DDOV 0
PVOE RSTDISBL
(1)
PVOV 0
PTOE 0
DIEOE (PCINT26 • PCIE3) + ADC26D + RSTDISBL
(1)
DIEOV PCINT26 • PCIE3 z RSTDISBL
(1)
DI PCINT26 Input
AIO ADC26 Input / RESET Input