Datasheet

ATtiny828 [DATASHEET]

8371A–AVR–08/12

Table 27. Alternative Functions of Port D

Note: 1. When TWEN in TWSCRA is set, this pin is disconnected from the port and becomes the serial data for the

TWI . In this mode of operation, the pin is driven by an open-drain circuit with slew rate limitation and spike

filter.

2. When SPI is enabled as a slave, this pin is automatically configured as an input, regardless of the data

direction bit of the pin. When SPI is enabled as a master normal pin control of data direction is resumed.

3. When SPI is enabled as a master, this pin is automatically configured as an input, regardless of the data

direction bit of the pin. When SPI is enabled as a slave normal pin control of data direction is resumed.

4. Enabled by unprogramming the RSTDISBL fuse. When used as a reset pin, the pin pullup resistor is acti-

vated and output driver and digital input are deactivated.

5. When TWEN in TWSCRA is set, this pin is disconnected from the port and becomes the serial clock for the

TWI. In this mode of operation, the pin is driven by an open-drain circuit with slew rate limitation and spike

filter.

Table 28, below, summarises the override signals used by the alternative functions of the port. For an illustration on how

signals are used, see Figure 25 on page 64.

Pin Function Description of Alternative Function

PD0

PCINT24 Pin change interrupt source

ADC24 Input channel for analog to digital converter (ADC)

SDA Two-Wire Interface (TWI) data

(1)

MOSI Master Output / Slave Input of SPI

(2)

PD1

PCINT25 Pin change interrupt source

ADC25 Input channel for analog to digital converter (ADC)

MISO Master Input / Slave Output of SPI

(3)

PD2

PCINT26 Pin change interrupt source

ADC26 Input channel for analog to digital converter (ADC)

RESET External reset input, active low

(4)

dW Input / Output of debugWire

PD3

PCINT27 Pin change interrupt source

ADC27 Input channel for analog to digital converter (ADC)

SCL Two-Wire Interface (TWI) clock

(5)

SCK Master clock output / slave clock input of SPI

(2)