Datasheet

78
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Notes: 1. XCK_MASTER = UMSEL1 z UMSEL0 + UMSEL0 z DDRC0
2. XCK_SLAVE = UMSEL1
z UMSEL0 z DDRC0
3. CKOUT is 1 when the fuse bit is “0” (programmed)
4. EXT_CLOCK means that external clock is selected (by the CKSEL fuses)
10.3.4 Alternative Functions of Port D
The alternative functions of port D are shown in Table 27.
PC6
PUOE 0
PUOV 0
DDOE EXT_CLOCK
(4)
DDOV 0
PVOE TOCC6OE + EXT_CLOCK
(4)
PVOV TOCC6_OUT z EXT_CLOCK
(4)
PTOE 0
DIEOE (PCINT22 • PCIE2) + ADC22D + EXT_CLOCK
(4)
DIEOV (EXT_CLOCK
(4)
• PWR_DOWN) + (EXT_CLOCK z PCINT22 z PCIE2)
DI PCINT22 Input / CLOCK
AIO ADC22 Input
PC7
PUOE 0
PUOV 0
DDOE 0
DDOV 0
PVOE TOCC7OE
PVOV TOCC7_OUT
PTOE 0
DIEOE (PCINT23 • PCIE2) + ADC23D
DIEOV PCINT23 • PCIE2
DI PCINT23 Input
AIO ADC23 Input / T1_IN
Pin Signal Composition