Datasheet

75
ATtiny828 [DATASHEET]
8371A–AVR–08/12
2. When SPI is enabled as a slave, this pin is automatically configured as an input, regardless of the data
direction bit of the pin. When SPI is enabled as a master normal pin control of data direction is resumed.
3. When the CKOUT fuse is programmed, the system clock is output on this pin, regardless of pin settings.
The clock is also output when the device is reset.
Table 26, below, summarises the override signals used by the alternative functions of the port. For an illustration on how
signals are used, see Figure 25 on page 64.
Table 26. Override Signals of Port C
Pin Signal Composition
PC0
PUOE 0
PUOV 0
DDOE SPE z MSTR
DDOV 0
PVOE TOCC0OE + XCK_MASTER
(1)
PVOV XCK_MASTER z XCK_OUT + XCK_MASTER z TOCC0_OUT
PTOE 0
DIEOE (PCINT16 • PCIE2) + ADC16D + (XCK_SLAVE
(2)
z RXEN z SFDE)
DIEOV (PCINT16 • PCIE2) + (XCK_SLAVE
(2)
z RXEN z SFDE)
DI PCINT16 Input / XCK_IN / SS Input
AIO ADC16 Input
PC1
PUOE 0
PUOV 0
DDOE CKOUT
(3)
DDOV CKOUT
(3)
PVOE 0TOCC1E + CKOUT
(3)
PVOV CKOUT
(3)
z SYSTEM_CLOCK + CKOUT z TOCC1_OUT
PTOE 0
DIEOE (PCINT17 • PCIE2) + ADC17D + INT0
DIEOV PCINT17 • PCIE2 + INT0
DI PCINT17 Input / INT0 Input
AIO ADC17 Input