Datasheet

62
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the
clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH”
signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the
succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin
will be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 24 on page
62. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through
the synchronizer is one system clock period.
Figure 24. Synchronization when Reading a Software Assigned Pin Value
10.2.4 Digital Input Enable and Sleep Modes
As shown in Figure 22 on page 60, the digital input signal can be clamped to ground at the input of the schmitt-trigger.
The signal denoted SLEEP in the figure, is set by the MCU sleep controller in Power-down and Standby modes to avoid
high power consumption if some input signals are left floating, or have an analog signal level close to V
CC
/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled,
SLEEP is active also for these pins. SLEEP is also overridden by various other alternative functions as described in
“Alternative Port Functions” on page 63.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge,
Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External
Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode
produces the requested logic change.
10.2.5 Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the
digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce
current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up
will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external
pull-up or pulldown. Connecting unused pins directly to V
CC
or GND is not recommended, since this may cause
excessive currents if the pin is accidentally configured as an output.
out PORTx, r16 nop in r17, PINx
0xFF
0x00 0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t
pd