Datasheet

61
ATtiny828 [DATASHEET]
8371A–AVR–08/12
The pull-up resistor is activated, if the PUExn is written logic one. To switch the pull-up resistor off, PUExn has to be
written logic zero.
Table 19 summarizes the control signals for the pin value.
Table 19. Port Pin Configurations
Port pins are tri-stated when a reset condition becomes active, even when no clocks are running.
10.2.2 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI
instruction can be used to toggle one single bit in a port.
10.2.3 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown
in Figure 22 on page 60, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to
avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay.
Figure 23 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum
and minimum propagation delays are denoted t
pd,max
and t
pd,min
respectively.
Figure 23. Synchronization when Reading an Externally Applied Pin value
DDxn PORTxn PUExn I/O Pull-up Comment
0 X 0 Input No Tri-state (hi-Z)
0 X 1 Input Yes Sources current if pulled low externally
1 0 0 Output No Output low (sink)
1 0 1 Output Yes
NOT RECOMMENDED.
Output low (sink) and internal pull-up active. Sources
current through the internal pull-up resistor and consumes
power constantly
1 1 0 Output No Output high (source)
1 1 1 Output Yes Output high (source) and internal pull-up active
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
t
pd, max
t
pd, min