Datasheet
57
ATtiny828 [DATASHEET]
8371A–AVR–08/12
z Bit 0 – INT0: External Interrupt Request 0 Enable
The external interrupt for pin INT0 is enabled when this bit and the I-bit in the Status Register (SREG) are set. The trigger
conditions are set with the ISC0n bits.
Activity on the pin will cause an interrupt request even if INT1 has been configured as an output.
9.3.9 EIFR – External Interrupt Flag Register
z Bits 7:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
z Bit 1 – INTF1: External Interrupt Flag 0
This bit is set when activity on INT1 has triggered an interrupt request. Provided that the I-bit in SREG and the INT1 bit in
EIMSK are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt service routine is executed. Alternatively, the flag can be cleared by writing a
logical one to it.
This flag is always cleared when INT1 is configured as a level interrupt.
z Bit 0 – INTF0: External Interrupt Flag 0
This bit is set when activity on INT0 has triggered an interrupt request. Provided that the I-bit in SREG and the INT0 bit in
EIMSK are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt service routine is executed. Alternatively, the flag can be cleared by writing a
logical one to it.
This flag is always cleared when INT0 is configured as a level interrupt.
9.3.10 PCIFR – Pin Change Interrupt Flag Register
z Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
z Bit 3 – PCIF3: Pin Change Interrupt Flag 3
This bit is set when a logic change on any PCINT[27:24] pin has triggered an interrupt request. Provided that the I-bit in
SREG and the PCIE3 bit in PCICR are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
Bit 76543210
0x1C (0x3C) ––––––INTF1INTF0EIFR
Read/Write RRRRRRR/WR/W
Initial Value 00000000
Bit 76543210
0x1B (0x3B) ––––PCIF3PCIF2PCIF1PCIF0PCIFR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 00000000