Datasheet

55
ATtiny828 [DATASHEET]
8371A–AVR–08/12
9.3.5 PCMSK0 – Pin Change Mask Register 0
z Bits 7:0 – PCINT[7:0] : Pin Change Interrupt Mask Bits
Each PCINTn bit selects if the pin change interrupt of the corresponding I/O pin is enabled. Pin change interrupt on a pin
is enabled by setting the mask bit for the pin (PCINTn) and the corresponding group bit (PCIEn) in PCICR.
When this bit is cleared the pin change interrupt on the corresponding pin is disabled.
9.3.6 EICRA – External Interrupt Control Register A
The External Interrupt Control Register contains bits for controlling external interrupt sensing and power management.
z Bits 3:2 – ISC11, ISC10: Interrupt Sense Control, INT1
z Bits 1:0 – ISC01, ISC00: Interrupt Sense Control, INT0
External interrupts INT0 and INT1 are triggered by activity on pin INT0 and INT1, provided that the SREG I-flag and the
corresponding interrupt mask are set. The conditions required to trigger the interrupt are defined in Table 18.
Table 18. External Interrupt Sense Control
Note: 1. If low level interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
2. The value on the INT0/INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected,
pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt.
Bit 76543210
(0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0x69) – – – – ISC11 ISC10 ISC01 ISC00 EICRA
Read/Write RRRRR/WR/WR/WR/W
Initial Value 00000000
ISCn1 ISCn0 Description
0 0 The low level of INT0/INT1 generates an interrupt request
(1)
0 1 Any logical change on INT0/INT1 generates an interrupt request
(2)
1 0 The falling edge of INT0/INT1 generates an interrupt request
(2)
1 1 The rising edge of INT0/INT1 generates an interrupt request
(2)