Datasheet

5
ATtiny828 [DATASHEET]
8371A–AVR–08/12
2. Overview
ATtiny828 is a low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the ATtiny828 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
Figure 3. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
DEBUG
INTERFACE
CALIBRATED ULP
OSCILLATOR
WATCHDOG
TIMER
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
V
CC
RESET
GND
8-BIT DATA BUS
PD[3:0]
CPU CORE
PROGRAM
MEMORY
(FLASH)
DATA
MEMORY
(SRAM)
POWER
SUPERVISION:
POR
BOD
RESET
ISP
INTERFACE
PORT A PORT B PORT C PORT D
VOLTAGE
REFERENCE
MULTIPLEXER
ANALOG
COMPARATOR
ADC
TEMPERATURE
SENSOR
8-BIT
TIMER/COUNTER
16-BIT
TIMER/COUNTER
TWO-WIRE
INTERFACE
USART
EEPROM
ON-CHIP
DEBUGGER
PC[7:0]PB[7:0]
PA[7:0]