Datasheet

47
ATtiny828 [DATASHEET]
8371A–AVR–08/12
If the watchdog timer is not going to be used in the application, it is important to go through a watchdog disable procedure
in the initialization of the device. If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out
condition, the device will be reset, which in turn will lead to a new watchdog reset. To avoid this situation, the application
software should always clear the WDRF flag and the WDE control bit in the initialization routine.
z Bits 5, 2:0 – WDP[3:0]: Watchdog Timer Prescaler 3 - 0
The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different
prescaling values and their corresponding Timeout Periods are shown in Table 15.
Table 15. Watchdog Timer Prescale Select
Note: 1. If selected, one of the valid settings below 0b1010 will be used.
To avoid unintentional changes of these bits, the following sequence must be followed:
1. Write the required signature to the CCP register. See page 14.
2. Within four instruction cycles, write the desired bit value.
WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at V
CC
= 5.0V
0 0 0 0 512 cycles 16 ms
0 0 0 1 1K cycles 32 ms
0 0 1 0 2K cycles 64 ms
0 0 1 1 4K cycles 0.125 s
0 1 0 0 8K cycles 0.25 s
0 1 0 1 16K cycles 0.5 s
0 1 1 0 32K cycles 1.0 s
0 1 1 1 64K cycles 2.0 s
1 0 0 0 128K cycles 4.0 s
1 0 0 1 256K cycles 8.0 s
1 0 1 0
Reserved
(1)
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1