Datasheet

ATtiny828 [DATASHEET]

8371A–AVR–08/12

To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUSR as early as

possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by

examining the Reset Flags.

8.5.2 WDTCSR – Watchdog Timer Control and Status Register

z Bit 7 – WDIF: Watchdog Timeout Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is

cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by

writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

z Bit 6 – WDIE: Watchdog Timeout Interrupt Enable

When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the Watchdog Time-out

Interrupt is enabled. In this mode the corresponding interrupt is executed instead of a reset if a timeout in the Watchdog

Timer occurs.

If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful for keeping the

Watchdog Reset security while using the interrupt. After the WDIE bit is cleared, the next time-out will generate a reset.

To avoid the Watchdog Reset, WDIE must be set after each interrupt.

Table 14. Watchdog Timer Configuration

z Bit 4 – Res: Reserved

This bit is reserved and will always read zero.

z Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the

Watchdog Timer function is disabled.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See “Timed

Sequences for Changing the Configuration of the Watchdog Timer” on page 44.

In safety level 1, WDE is overridden by WDRF in MCUSR. See “MCUSR – MCU Status Register” on page 45 for

description of WDRF. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared

before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during

conditions causing failure, and a safe start-up after the failure.

Bit 76543210

(0x60) WDIF WDIE WDP3 – WDE WDP2 WDP1 WDP0 WDTCSR

Read/Write R/WR/WR/WR/WR/WR/WR/WR/W

Initial Value 0 0 0 0 X 0 0 0

WDE WDIE Watchdog Timer State Action on Time-out

0 0 Stopped None

0 1 Running Interrupt

1 0 Running Reset

1 1 Running Interrupt