Datasheet

ATtiny828 [DATASHEET]

8371A–AVR–08/12

Figure 19. Watchdog Timer

8.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are

described for each level.

z Safety Level 1

In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without

any restriction. A timed sequence is needed when disabling an enabled Watchdog Timer. To disable an enabled

Watchdog Timer, the following procedure must be followed:

1. Write the signature for change enable of protected I/O registers to register CCP

2. Within four instruction cycles, in the same operation, write WDE and WDP bits

z Safety Level 2

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence

is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following proce-

dure must be followed:

1. Write the signature for change enable of protected I/O registers to register CCP

2. Within four instruction cycles, write the WDP bit. The value written to WDE is irrelevant

8.4.2 Code Examples

The following code example shows how to turn off the WDT. The example assumes that interrupts are controlled (e.g., by

disabling interrupts globally) so that no interrupts will occur during execution of these functions.

OSC/512

OSC/1K

OSC/2K

OSC/4K

OSC/8K

OSC/16K

OSC/32K

OSC/64K

OSC/128K

OSC/256K

MCU RESET

WATCHDOG

PRESCALER

32 kHz

ULP OSCILLATOR

WATCHDOG

RESET

WDP0

WDP1

WDP2

WDP3

WDE

MUX