Datasheet

37
ATtiny828 [DATASHEET]
8371A–AVR–08/12
7.4 Register Description
7.4.1 SMCR – Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
z Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
z Bits 2:1 – SM[1:0]: Sleep Mode Select Bits 1 and 0
These bits select the sleep mode, as shown in Table 10.
Table 10. Sleep Mode Select
z Bit 0 – SE: Sleep Enable
This bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To
avoid the MCU entering sleep mode unintentionally, it is recommended to write the Sleep Enable (SE) bit to one just
before the execution of the SLEEP instruction and to clear it immediately after waking up.
7.4.2 PRR – Power Reduction Register
The Power Reduction Register provides a method to reduce power consumption by allowing peripheral clock signals to
be disabled.
z Bit 7 – PRTWI: Power Reduction Two-Wire Interface
Writing a logic one to this bit shuts down the Two-Wire Interface module.
z Bits 6, 4 – Res: Reserved Bits
These bits are reserved and will always read zero.
z Bit 5 – PRTIM0: Power Reduction Timer/Counter0
Bit 76543210
0x33 (0x53) –––––SM1SM0SESMCR
Read/Write RRRRRR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0
SM1 SM0 Sleep Mode
0 0 Idle
0 1 ADC Noise Reduction
1 0 Power-down
1 1 Reserved
Bit 76543 2 1 0
(0x64) PRTWI – PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC PRR
Read/Write R/W R R/W R R/W R/W R/W R/W
Initial Value00000 0 0 0