Datasheet

36
ATtiny828 [DATASHEET]
8371A–AVR–08/12
possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following
modules may need special consideration when trying to achieve the lowest possible power consumption.
7.3.1 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any
sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. See “Analog
to Digital Converter” on page 137 for details on ADC operation.
7.3.2 Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction
mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically
disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog
Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled,
independent of sleep mode. See “Analog Comparator” on page 133 for details on how to configure the Analog
Comparator.
7.3.3 Brown-out Detector
If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is
enabled by the BODPD Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper
sleep modes, this will contribute significantly to the total current consumption. If the Brown-out Detector is needed in the
application, this module can also be set to Sampled BOD mode to save power. See “Brown-out Detection” on page 41 for
details on how to configure the Brown-out Detector.
7.3.4 Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the
ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled
and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output
is used. If the reference is kept on in sleep mode, the output can be used immediately. See Internal Bandgap Reference
in Table 107 on page 250 for details on the start-up time.
7.3.5 Watchdog Timer
If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is
enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will
contribute to the total current consumption. See “Brown-out Detection” on page 41 for details on how to configure the
Watchdog Timer.
7.3.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then
to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk
I/O
) and the ADC clock (clk
ADC
)
are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic
when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled.
See the section “Digital Input Enable and Sleep Modes” on page 62 for details on which pins are enabled. If the input
buffer is enabled and the input signal is left floating or has an analog signal level close to V
CC
/2, the input buffer will use
excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V
CC
/2 on an
input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital
Input Disable Register (DIDR0). See “DIDR3 – Digital Input Disable Register 3” on page 154 for details.