Datasheet

31
ATtiny828 [DATASHEET]
8371A–AVR–08/12
5. At least 4ms when reset is disabled.
6.6 Register Description
6.6.1 CLKPR – Clock Prescale Register
z Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
z Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits can be
written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock
input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors
are given in Table 8.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
Table 8. Clock Prescaler Select
Bit 76543210
(0x61) – – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 See Bit Description
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
0 0 0 0 1
(1)
0 0 0 1 2
0 0 1 0 4
0 0 1 1 8
(2)
0 1 0 0 16
0 1 0 1 32
0 1 1 0 64
0 1 1 1 128
1 0 0 0 256
1 0 0 1 Reserved
1 0 1 0 Reserved
1 0 1 1 Reserved
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved