Datasheet

306
ATtiny828 [DATASHEET]
8371A–AVR–08/12
30. Errata
The revision letters in this section refer to the revision of the corresponding ATtiny828 device.
30.1 Rev. A
z Port Pin Restrictions When ULP Oscillator Is Disabled
1. Port Pin Restrictions When ULP Oscillator Is Disabled
Port pin PD3 is not guaranteed to perform as a reliable input when the Ultra Low Power (ULP) oscillator is not run-
ning. In addition, the pin is pulled down internally when ULP oscillator is disabled. TWI and SPI use may be limited
when ULP is not running since pin PD3 is used by SCL and SCK signals.
Problem Fix / Workaround
The ULP oscillator is automatically activated when required. To use PD3 as an input or clock signal of TWI/SPI,
activate the watchdog timer. The watchdog timer automatically enables the ULP oscillator.