Datasheet

30
ATtiny828 [DATASHEET]
8371A–AVR–08/12
6.3 System Clock Prescaler
The ATtiny828 system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 31. This feature
can be used to decrease power consumption when the requirement for processing power is low. This can be used with
all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk
I/O
, clk
ADC
,
clk
CPU
, and clk
FLASH
are divided by a factor as shown in Table 8 on page 31.
6.3.1 Switching Prescaler Setting
When switching between prescaler settings, the System Clock Prescaler ensures that no glitch occurs in the clock
system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous
setting, nor the clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than
the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and
the exact time it takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is
active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period
corresponding to the new prescaler setting.
6.4 Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT fuse has to be programmed.
This mode is suitable when the chip clock is used to drive other circuits on the system. Note that the clock will not be
output during reset and that the normal operation of the I/O pin will be overridden when the fuse is programmed. Any
clock source, including the internal oscillators, can be selected when the clock is output on CLKO. If the System Clock
Prescaler is used, it is the divided system clock that is output.
6.5 Start-Up Time
The CKSEL and SUT fuse bits define the start-up time of the device, as shown in Table 7 on page 30, below.
Table 7. CKSEL and SUT Fuse Bits vs. Device Start-up Time
Note: 1. Device start-up time from power-down sleep mode.
2. When BOD has been disabled by software, the wake-up time from sleep mode will be approximately 60µs to
ensure the BOD is working correctly before MCU continues executing code.
3. Device start-up time after reset.
4. The device is shipped with this option selected.
CKSEL SUT Clock From Power-Down
(1)(2)
From Reset
(3)
0X
00
External 6 CK
20 CK
01 20 CK + 4ms
1X 20 CK + 64ms
10
(4)
00
Internal 8MHz
6 CK
(5)
20 CK
(5)
01 20 CK + 4ms
1X
(4)
20 CK + 64ms
11
00
Internal 32kHz
20 CK
(5)
01 20 CK + 4ms
1X 20 CK + 64ms