Datasheet

28
ATtiny828 [DATASHEET]
8371A–AVR–08/12
6.1.4 ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise
generated by digital circuitry. This gives more accurate ADC conversion results.
6.2 Clock Sources
The device can use any of the following sources for the system clock:
z External Clock (see page 28)
z Calibrated Internal 8MHz Oscillator (see page 29)
z Internal 32kHz Ultra Low Power (ULP) Oscillator (see page 29)
The clock source is selected using CKSEL fuses, as shown in Table 6 below.
Table 6. CKSEL Fuse Bits and Device Clocking Options
Note: 1. For all fuses “1” means unprogrammed and “0” means programmed.
2. This is the default setting. The device is shipped with this fuse combination.
.
CKSEL fuse bits can be read by firmware (see “Reading Lock, Fuse and Signature Data from Software” on page 229),
but firmware can not write to fuse bits.
When the device wakes up from power-down the selected clock source is used to time the start-up, ensuring stable
oscillator operation before instruction execution starts. When the CPU starts from reset, the internal 32kHz oscillator is
used for generating an additional delay, allowing supply voltage to reach a stable level before normal device operation is
started.
System clock alternatives are discussed in the following sections.
6.2.1 External Clock
To drive the device from an external clock source, CLKI should be connected as shown in Figure 12, below.
Figure 12. External Clock Drive Configuration
Start-up time for this clock source is determined by the SUT fuse bit, as shown in Table 7 on page 30.
CKSEL[1:0]
(1)
Frequency Device Clocking Option
0X Any External Clock (see page 28)
10 8MHz Calibrated Internal 8MHz Oscillator (see page 29)
(2)
11 32kHz Internal 32kHz Ultra Low Power (ULP) Oscillator (see page 29)
EXTERNAL
CLOCK
SIGNAL
CLKI
GND