Datasheet

25
ATtiny828 [DATASHEET]
8371A–AVR–08/12
z Bit 2 – EEMPE: EEPROM Master Program Enable
The EEMPE bit determines whether writing EEPE to one will have effect or not.
When EEMPE is set and EEPE written within four clock cycles the EEPROM at the selected address will be
programmed. Hardware clears the EEMPE bit to zero after four clock cycles.
If EEMPE is zero the EEPE bit will have no effect.
z Bit 1 – EEPE: EEPROM Program Enable
This is the programming enable signal of the EEPROM. The EEMPE bit must be set before EEPE is written, or EEPROM
will not be programmed.
When EEPE is written, the EEPROM will be programmed according to the EEPMn bit settings. When EEPE has been
set, the CPU is halted for two cycles before the next instruction is executed. After the write access time has elapsed, the
EEPE bit is cleared by hardware.
Note that an EEPROM write operation blocks all software programming of Flash, fuse bits, and lock bits.
z Bit 0 – EERE: EEPROM Read Enable
This is the read strobe of the EEPROM. When the target address has been set up in the EEAR, the EERE bit must be
written to one to trigger the EEPROM read operation.
EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is
read, the CPU is halted for four cycles before the next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it not possible to
read the EEPROM, or to change the address register (EEAR).
5.4.4 GPIOR2 – General Purpose I/O Register 2
This register may be used freely for storing any kind of data.
5.4.5 GPIOR1 – General Purpose I/O Register 1
This register may be used freely for storing any kind of data.
Bit 76543210
0x2B (0x4B) MSB LSB GPIOR2
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x2A (0x4A) MSB LSB GPIOR1
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0