Datasheet

243
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Table 100. Pin Mapping Serial Programming
23.3.2 Programming Algorithm
When writing serial data to the ATtiny828, data is clocked on the rising edge of SCK. When reading data from the
ATtiny828, data is clocked on the falling edge of SCK. See Figure 107 on page 257 and Figure 108 on page 257 for
timing details.
To program and verify the ATtiny828 in the serial programming mode, the following sequence is recommended (See
Table 101 on page 244):
1. Power-up sequence: apply power between V
CC
and GND while RESET and SCK are set to “0”
z In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case,
RESET
must be given a positive pulse after SCK has been set to '0'. The duration of the pulse must be at
least t
RST
plus two CPU clock cycles. See Table 107 on page 250 for definition of minimum pulse width on
RESET
pin, t
RST
2. Wait for at least 20 ms and then enable serial programming by sending the Programming Enable serial instruction
to the MOSI pin
3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the
second byte (0x53) will echo back when issuing the third byte of the Programming Enable instruction
z Regardless if the echo is correct or not, all four bytes of the instruction must be transmitted
z If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6
LSB of the address and data together with the Load Program Memory Page instruction
z To ensure correct loading of the page, data low byte must be loaded before data high byte for a given
address is applied
z The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7
MSB of the address
z If polling (RDY/BSY) is not used, the user must wait at least t
WD_FLASH
before issuing the next page (See
Table 102 on page 246). Accessing the serial programming interface before the Flash write operation
completes can result in incorrect programming.
5. The EEPROM can be programmed one byte or one page at a time.
z A: Byte programming. The EEPROM array is programmed one byte at a time by supplying the address and
data together with the Write instruction. EEPROM memory locations are automatically erased before new
data is written. If polling (RDY/BSY
) is not used, the user must wait at least t
WD_EEPROM
before issuing the
next byte (See Table 102 on page 246). In a chip erased device, no 0xFFs in the data file(s) need to be
programmed
z B: Page programming (the EEPROM array is programmed one page at a time). The memory page is loaded
one byte at a time by supplying the 6 LSB of the address and data together with the Load EEPROM Memory
Page instruction. The EEPROM memory page is stored by loading the Write EEPROM Memory Page
Instruction with the 7 MSB of the address. When using EEPROM page access only byte locations loaded
with the Load EEPROM Memory Page instruction are altered and the remaining locations remain
unchanged. If polling (RDY/BSY
) is not used, the user must wait at least t
WD_EEPROM
before issuing the next
byte (See Table 102 on page 246). In a chip erased device, no 0xFF in the data file(s) need to be
programmed
Symbol Pins I/O Description
MOSI PD0 I Serial Data in
MISO PD1 O Serial Data out
SCK PD3 I Serial Clock