Datasheet

242
ATtiny828 [DATASHEET]
8371A–AVR–08/12
Figure 99. Serial Programming Signals
Notes: 1. If the device is clocked by the internal oscillator there is no need to connect a clock source to the CLKI pin.
2. V
CC
- 0.3V < AV
CC
< V
CC
+ 0.3V, however, AV
CC
should always be within 1.7 – 5.5V.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation and there is no
need to first execute the Chip Erase instruction. This applies for serial programming mode, only.
The Chip Erase operation turns the content of every memory location in Flash and EEPROM arrays into 0xFF.
Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK)
input are defined as follows:
z Minimum low period of serial clock:
z When f
ck
< 12MHz: > 2 CPU clock cycles
z When f
ck
>= 12MHz: 3 CPU clock cycles
z Minimum high period of serial clock:
z When f
ck
< 12MHz: > 2 CPU clock cycles
z When f
ck
>= 12MHz: 3 CPU clock cycles
23.3.1 Pin Mapping
The pin mapping is listed in Table 100 on page 243. Note that not all parts use the SPI pins dedicated for the internal SPI
interface.
VCC
GND
CLKI
(1)
SCK
MISO
MOSI
RESET
+1.8 - 5.5V
AVCC
+1.8 - 5.5V
(2)