Datasheet

223
ATtiny828 [DATASHEET]
8371A–AVR–08/12
21.10 Programming Time for Flash when Using SPM
Flash access is timed using the internal, calibrated 8MHz oscillator. Typical Flash programming times for the CPU are
shown in Table 84.
Table 84. SPM Programming Time
Note: 1. Min and max programming times are per individual operation.
21.11 Register Description
21.11.1 SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory
operations.
z Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be
enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit is cleared.
z Bit 6 – RWWSB: Read-While-Write Section Busy
When this bit is set, the RWW section cannot be accessed.
This bit is set when a self-programming operation (Page Erase or Page Write) to the RWW section is initiated.
This bit is cleared if the RWWSRE bit is written to one after a self-programming operation is completed. This bit is
automatically cleared when a page load operation is initiated.
z Bit 5 – RSIG: Read Device Signature Imprint Table
Issuing an LPM instruction within three cycles after RSIG and SPMEN bits have been set in SPMCSR will return the
selected data (depending on Z-pointer value) from the device signature imprint table into the destination register. See
“Device Signature Imprint Table” on page 228 for details.
z Bit 4 – RWWSRE: Read-While-Write Section Read Enable
The RWW section is blocked for reading (see RWWSB bit) when the section is being programmed. To re-enable the
section, the software must first wait until the programming is completed (see SPMEN bit). The RWW section is then re-
enabled by simultaneously writing bits RWWSRE and SPMEN and, within four clock cycles, issuing an SPM instruction.
The RWW section cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write operation (see
SPMEN). If the RWWSRE bit is written while the Flash is being loaded, the operation will abort and the data will be lost.
Operation Min
(1)
Max
(1)
SPM: Flash Page Erase, Flash Page Write, and lock bit write 3.7 ms 4.5 ms
Bit 7 6 5 4 3 2 1 0
0x37 (0x57) SPMIE RWWSB RSIG RWWSRE RWFLB PGWRT PGERS SPMEN SPMCSR
Read/Write R/W R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0