Datasheet

211
ATtiny828 [DATASHEET]
8371A–AVR–08/12
19.5.5 TWSD – TWI Slave Data Register
The data register is used when transmitting and received data. During transfer, data is shifted from/to the TWSD register
and to/from the bus. Therefore, the data register cannot be accessed during byte transfers. This is protected in hardware.
The data register can only be accessed when the SCL line is held low by the slave, i.e. when TWCH is set.
When a master reads data from a slave, the data to be sent must be written to the TWSD register. The byte transfer is
started when the master starts to clock the data byte from the slave. It is followed by the slave receiving the acknowledge
bit from the master. The TWDIF and the TWCH bits are then set.
When a master writes data to a slave, the TWDIF and the TWCH flags are set when one byte has been received in the
data register. If Smart Mode is enabled, reading the data register will trigger the bus operation, as set by the TWAA bit in
TWSCRB.
Accessing TWSD will clear the slave interrupt flags and the TWCH bit.
19.5.6 TWSAM – TWI Slave Address Mask Register
z Bits 7:1 – TWSAM[7:1]: TWI Address Mask
These bits can act as a second address match register, or an address mask register, depending on the TWAE setting.
If TWAE is set to zero, TWSAM can be loaded with a 7-bit slave address mask. Each bit in TWSAM can mask (disable)
the corresponding address bit in the TWSA register. If the mask bit is one the address match between the incoming
address bit and the corresponding bit in TWSA is ignored. In other words, masked bits will always match.
If TWAE is set to one, TWSAM can be loaded with a second slave address in addition to the TWSA register. In this
mode, the slave will match on 2 unique addresses, one in TWSA and the other in TWSAM.
z Bit 0 – TWAE: TWI Address Enable
By default, this bit is zero and the TWSAM bits acts as an address mask to the TWSA register. If this bit is set to one, the
slave address match logic responds to the two unique addresses in TWSA and TWSAM.
Bit 76543210
(0xBD) TWSD[7:0] TWSD
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
(0xBB) TWSAM[7:1] TWAE TWSAM
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0