Datasheet

210
ATtiny828 [DATASHEET]
8371A–AVR–08/12
This bit is read-only. When zero, the most recent acknowledge bit from the maser was ACK and, when one, the most
recent acknowledge bit was NACK.
z Bit 3 – TWC: TWI Collision
This bit is set when the slave was not able to transfer a high data bit or a NACK bit. When a collision is detected, the
slave will commence its normal operation, and disable data and acknowledge output. No low values are shifted out onto
the SDA line.
This bit is cleared by writing a one to it. The bit is also cleared automatically when a START or Repeated START
condition is detected.
z Bit 2 – TWBE: TWI Bus Error
This bit is set when an illegal bus condition has occured during a transfer. An illegal bus condition occurs if a Repeated
START or STOP condition is detected, and the number of bits from the previous START condition is not a multiple of
nine.
This bit is cleared by writing a one to it.
z Bit 1 – TWDIR: TWI Read/Write Direction
This bit indicates the direction bit from the last address packet received from a master. When this bit is one, a master
read operation is in progress. When the bit is zero a master write operation is in progress.
z Bit 0 – TWAS: TWI Address or Stop
This bit indicates why the TWASIF bit was last set. If zero, a stop condition caused TWASIF to be set. If one, address
detection caused TWASIF to be set.
19.5.4 TWSA – TWI Slave Address Register
The slave address register contains the TWI slave address used by the slave address match logic to determine if a
master has addressed the slave. When using 7-bit or 10-bit address recognition mode, the high seven bits of the address
register (TWSA[7:1]) represent the slave address. The least significant bit (TWSA0) is used for general call address
recognition. Setting TWSA0 enables general call address recognition logic.
When using 10-bit addressing the address match logic only support hardware address recognition of the first byte of a
10-bit address. If TWSA[7:1] is set to "0b11110nn", 'nn' will represent bits 9 and 8 of the slave address. The next byte
received is then bits 7 to 0 in the 10-bit address, but this must be handled by software.
When the address match logic detects that a valid address byte has been received, the TWASIF is set and the TWDIR
flag is updated.
If TWPME in TWSCRA is set, the address match logic responds to all addresses transmitted on the TWI bus. TWSA is
not used in this mode.
Bit 76543210
(0xBC) TWSA[7:0] TWSA
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0