Datasheet

207
ATtiny828 [DATASHEET]
8371A–AVR–08/12
19.5 Register Description
19.5.1 TWSCRA – TWI Slave Control Register A
z Bit 7 – TWSHE: TWI SDA Hold Time Enable
When this bit is set the internal hold time on SDA with respect to the negative edge on SCL is enabled.
z Bit 6 – Res: Reserved Bit
This bit is reserved and will always read as zero.
z Bit 5 – TWDIE: TWI Data Interrupt Enable
When this bit is set and interrupts are enabled, a TWI interrupt will be generated when the data interrupt flag (TWDIF) in
TWSSRA is set.
z Bit 4 – TWASIE: TWI Address/Stop Interrupt Enable
When this bit is set and interrupts are enabled, a TWI interrupt will be generated when the address/stop interrupt flag
(TWASIF) in TWSSRA is set.
z Bit 3 – TWEN: Two-Wire Interface Enable
When this bit is set the slave Two-Wire Interface is enabled.
z Bit 2 – TWSIE: TWI Stop Interrupt Enable
Setting the Stop Interrupt Enable (TWSIE) bit will set the TWASIF in the TWSSRA register when a STOP condition is
detected.
z Bit 1 – TWPME: TWI Promiscuous Mode Enable
When this bit is set the address match logic of the slave TWI responds to all received addresses. When this bit is cleared
the address match logic uses the TWSA register to determine which address to recognize as its own.
z Bit 0 – TWSME: TWI Smart Mode Enable
When this bit is set the TWI slave enters Smart Mode, where the Acknowledge Action is sent immediately after the TWI
data register (TWSD) has been read. Acknowledge Action is defined by the TWAA bit in TWSCRB.
When this bit is cleared the Acknowledge Action is sent after TWCMDn bits in TWSCRB are written to 1X.
Bit 76543210
(0xB8) TWSHE – TWDIE TWASIE TWEN TWSIE TWPME TWSME TWSCRA
Read/Write R/W R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0