Datasheet

202
ATtiny828 [DATASHEET]
8371A–AVR–08/12
19.3.4 Address Packet
After the START condition, a 7-bit address followed by a read/write (R/W) bit is sent. This is always transmitted by the
Master. A slave recognizing its address will ACK the address by pulling the data line low the next SCL cycle, while all
other slaves should keep the TWI lines released, and wait for the next START and address. The 7-bit address, the R/W
bit and the acknowledge bit combined is the address packet. Only one address packet for each START condition is
given, also when 10-bit addressing is used.
The R/W
specifies the direction of the transaction. If the R/W bit is low, it indicates a Master Write transaction, and the
master will transmit its data after the slave has acknowledged its address. Opposite, for a Master Read operation the
slave will start to transmit data after acknowledging its address.
19.3.5 Data Packet
Data packets succeed an address packet or another data packet. All data packets are nine bits long, consisting of one
data byte and an acknowledge bit. The direction bit in the previous address packet determines the direction in which the
data is transferred.
19.3.6 Transaction
A transaction is the complete transfer from a START to a STOP condition, including any Repeated START conditions in
between. The TWI standard defines three fundamental transaction modes: Master Write, Master Read, and combined
transaction.
Figure 82 illustrates the Master Write transaction. The master initiates the transaction by issuing a START condition (S)
followed by an address packet with direction bit set to zero (ADDRESS+W
).
Figure 82. Master Write Transaction
Given that the slave acknowledges the address, the master can start transmitting data (DATA) and the slave will ACK or
NACK (A/A
) each byte. If no data packets are to be transmitted, the master terminates the transaction by issuing a STOP
condition (P) directly after the address packet. There are no limitations to the number of data packets that can be
transferred. If the slave signal a NACK to the data, the master must assume that the slave cannot receive any more data
and terminate the transaction.
Figure 83 illustrates the Master Read transaction. The master initiates the transaction by issuing a START condition
followed by an address packet with direction bit set to one (ADRESS+R). The addressed slave must acknowledge the
address for the master to be allowed to continue the transaction.
Figure 83. Master Read Transaction