Datasheet

201
ATtiny828 [DATASHEET]
8371A–AVR–08/12
The master provides the clock signal for the transaction, but a device connected to the bus is allowed to stretch the low
level period of the clock to decrease the clock speed.
19.3.1 Electrical Characteristics
The TWI follows the electrical specifications and timing of I
2
C and SMBus. See “Two-Wire Serial Interface
Characteristics” on page 252 and “Compatibility with SMBus” on page 205.
19.3.2 START and STOP Conditions
Two unique bus conditions are used for marking the beginning (START) and end (STOP) of a transaction. The master
issues a START condition(S) by indicating a high to low transition on the SDA line while the SCL line is kept high. The
master completes the transaction by issuing a STOP condition (P), indicated by a low to high transition on the SDA line
while SCL line is kept high.
Figure 80. START and STOP Conditions
Multiple START conditions can be issued during a single transaction. A START condition not directly following a STOP
condition, are named a Repeated START condition (Sr).
19.3.3 Bit Transfer
As illustrated by Figure 81 a bit transferred on the SDA line must be stable for the entire high period of the SCL line.
Consequently the SDA value can only be changed during the low period of the clock. This is ensured in hardware by the
TWI module.
Figure 81. Data Validity
Combining bit transfers results in the formation of address and data packets. These packets consist of 8 data bits (one
byte) with the most significant bit transferred first, plus a single bit not-acknowledge (NACK) or acknowledge (ACK)
response. The addressed device signals ACK by pulling the SCL line low, and NACK by leaving the line SCL high during
the ninth clock cycle.